Reconfigurable Parser Architecture Design with Microprogrammed Controller for Multiple Purposes

This paper utilizes the flexibility of microprogrammed controller with reloadable microcodes for developing reconfigurable parser for multiple purposes. Based on control-dataflow, with microprogrammed controller taken into consideration due to the nature of feedback control in parser, this paper proposes a reconfigurable parser through extracting control commonalities to form shared microinstructions so that the current architecture alleviates the cost in switching control signals for distinct purposes. We employ reconfigurable video coding as a case study to justify the advantages in reconfigurable parser with microprogrammed controller in comparison with finite state machine based controller. Using TSMC 0.18 μm CMOS technology at 108 MHz operating frequency, we reduce 8.93 % gate counts and increase throughput rate twice in comparison with individually implemented finite state machine based controller. We have demonstrated that microprogrammed controller is the trend of flexible architecture design for multiple purposes. Owing to high proportion of shared microinstruction, the higher saving ratio could be envision when multiple purposes are involved in the proposed reconfigurable parser, e.g., more video coding standards.