Reducing test application time and power dissipation for scan-based testing via multiple clock disabling

Kuen-Jong Lee, Jih Jeen Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Two problems that are becoming quite critical for scan-based testing are long test application time and high test power consumption. Previously, many efficient methods have been developed to address these two problems separately. In this paper, we propose a novel method called the multiple clock disabling (MCD) technique to reduce test application time and test power dissipation simultaneously. Our method is made possible by cleverly employing a number of existing techniques to generate a special set of test patterns that is suitable for a scan architecture based on the MCD technique. Experimental results show that on average 81% and 85% reductions in test application time and power dissipation have been respectively obtained when comparing to the conventional scan method.

Original languageEnglish
Title of host publicationProceedings of the 11th Asian Test Symposium, ATS 2002
PublisherIEEE Computer Society
Pages338-343
Number of pages6
ISBN (Electronic)0769518257, 0769518257
DOIs
Publication statusPublished - 2002 Jan 1
Event11th Asian Test Symposium, ATS 2002 - Guam, United States
Duration: 2002 Nov 182002 Nov 20

Publication series

NameProceedings of the Asian Test Symposium
Volume2002-January
ISSN (Print)1081-7735

Other

Other11th Asian Test Symposium, ATS 2002
CountryUnited States
CityGuam
Period02-11-1802-11-20

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Lee, K-J., & Chen, J. J. (2002). Reducing test application time and power dissipation for scan-based testing via multiple clock disabling. In Proceedings of the 11th Asian Test Symposium, ATS 2002 (pp. 338-343). [1181734] (Proceedings of the Asian Test Symposium; Vol. 2002-January). IEEE Computer Society. https://doi.org/10.1109/ATS.2002.1181734