TY - GEN
T1 - Reduction of detected acceptable faults for yield improvement via error-tolerance
AU - Hsieh, Tong Yu
AU - Lee, Kuen Jong
AU - Breuer, Melvin A.
PY - 2007
Y1 - 2007
N2 - Error-tolerance is an innovative way to enhance the effective yield of IC products. Previously a test methodology based on error-rate estimation to support error-tolerance was proposed. Without violating the system error-rate constraint specified by the user, this methodology identifies a set of faults that can be ignored during testing, thereby leading to a significant improvement in yield. However, usually the patterns detecting all of the unacceptable faults also detect a large number of acceptable faults, resulting in a degradation in achievable yield improvement. In this paper, we first provide a probabilistic analysis of this problem and show that a conventional ATPG procedure cannot adequately address this problem. We then present a novel test pattern selection procedure and an output masking technique to deal with this problem. The selection process generates a test set aimed to detect all unacceptable faults but as few acceptable faults as possible. The masking technique then examines the generated test patterns and identifies a list of output lines that can be masked (not observed) during testing so as to further avoid the detection of acceptable faults. Experimental results show that by employing the proposed techniques, only a small number of acceptable faults are still detected. In many cases the actual yield improvement approaches the optimal value that can be achieved.
AB - Error-tolerance is an innovative way to enhance the effective yield of IC products. Previously a test methodology based on error-rate estimation to support error-tolerance was proposed. Without violating the system error-rate constraint specified by the user, this methodology identifies a set of faults that can be ignored during testing, thereby leading to a significant improvement in yield. However, usually the patterns detecting all of the unacceptable faults also detect a large number of acceptable faults, resulting in a degradation in achievable yield improvement. In this paper, we first provide a probabilistic analysis of this problem and show that a conventional ATPG procedure cannot adequately address this problem. We then present a novel test pattern selection procedure and an output masking technique to deal with this problem. The selection process generates a test set aimed to detect all unacceptable faults but as few acceptable faults as possible. The masking technique then examines the generated test patterns and identifies a list of output lines that can be masked (not observed) during testing so as to further avoid the detection of acceptable faults. Experimental results show that by employing the proposed techniques, only a small number of acceptable faults are still detected. In many cases the actual yield improvement approaches the optimal value that can be achieved.
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U2 - 10.1109/DATE.2007.364530
DO - 10.1109/DATE.2007.364530
M3 - Conference contribution
AN - SCOPUS:34548336648
SN - 3981080122
SN - 9783981080124
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 1599
EP - 1604
BT - Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007
T2 - 2007 Design, Automation and Test in Europe Conference and Exhibition
Y2 - 16 April 2007 through 20 April 2007
ER -