TY - GEN
T1 - Reduction of surface recombination current by optimized ledge technology
AU - Chu, K. Y.
AU - Chen, L. Y.
AU - Chen, T. P.
AU - Hung, C. W.
AU - Tsai, T. H.
AU - Chen, L. A.
AU - Cheng, S. Y.
AU - Liu, Wen-Chau
PY - 2007/12/1
Y1 - 2007/12/1
N2 - In this work, the influence of various emitter ledge thicknesses on the performances of InGaP/GaAs heterojunction bipolar transistors is investigated based on the simulation data. The undesired surface channel phenomenon at the exposed base surface between base contact and emitter ledge is comprehensively analyzed. Moreover, improper thickness of emitter ledge passivation would cause serious surface recombination at the edge of emitter ledge. If the emitter ledge is too thick, current will flow through the undepleted ledge, which increases the emitter-size effect. In contrast, if the emitter ledge is too thin, it may not effectively passivate the surface. Therefore, the thickness of emitter ledge is a critical and should be carefully considered. From simulated results, the optimum emitter ledge thickness of InGaP/GaAs HBT is 100-200 Å.
AB - In this work, the influence of various emitter ledge thicknesses on the performances of InGaP/GaAs heterojunction bipolar transistors is investigated based on the simulation data. The undesired surface channel phenomenon at the exposed base surface between base contact and emitter ledge is comprehensively analyzed. Moreover, improper thickness of emitter ledge passivation would cause serious surface recombination at the edge of emitter ledge. If the emitter ledge is too thick, current will flow through the undepleted ledge, which increases the emitter-size effect. In contrast, if the emitter ledge is too thin, it may not effectively passivate the surface. Therefore, the thickness of emitter ledge is a critical and should be carefully considered. From simulated results, the optimum emitter ledge thickness of InGaP/GaAs HBT is 100-200 Å.
UR - http://www.scopus.com/inward/record.url?scp=43049171842&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=43049171842&partnerID=8YFLogxK
U2 - 10.1109/EDSSC.2007.4450228
DO - 10.1109/EDSSC.2007.4450228
M3 - Conference contribution
AN - SCOPUS:43049171842
SN - 1424406374
SN - 9781424406371
T3 - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
SP - 725
EP - 728
BT - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
T2 - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
Y2 - 20 December 2007 through 22 December 2007
ER -