Redundancy architectures for channel-based 3D DRAM yield improvement

Bing Yang Lin, Wan Ting Chiang, Cheng Wen Wu, Mincent Lee, Hung Chih Lin, Ching Nen Peng, Min Jer Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The three-dimensional integrated circuit (3D IC) is considered a promising approach that can obtain high data band-width and low power consumption for future electronic systems that require high integration level. One of the popular drivers for 3D IC is the integration of a memory stack and a logic die. Because the yield of a 3D IC is the product of respective yields of the mounted dies, the yields of the memory dies and logic die must be high enough, or the 3D IC will be too expensive to be manufactured. To obtain a high yield of 3D ICs, efficient test and repair methodologies for memories are necessary. In this paper, we target the channel-based 3D dynamic random access memory (DRAM) and propose two 3D redundancy architectures, i.e., Cubical Redundancy Architectures 1 and 2 (CRA1 and CRA2). We use Wide-IO DRAM as an example for discussion. In CRA1, spares are associated with each DRAM die as in a conven-tional 2D architecture. In CRA2, we use a static random access memory (SRAM) on the logic die as spares. Experimental results show that the CRA1 can achieve up to 18% higher stack yield than traditional redundancy architecture with the same area overhead. On the other hand, the CRA2 can achieve the same yield as the CRA1 with 40% less spares, but 1.3% higher area overhead.

Original languageEnglish
Title of host publicationProceedings - 2014 IEEE International Test Conference, ITC 2014
Place of PublicationSeattle, Washington
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479947225
DOIs
Publication statusPublished - 2015 Feb 6
Event45th IEEE International Test Conference, ITC 2014 - Seattle, United States
Duration: 2014 Oct 212014 Oct 23

Publication series

NameProceedings - International Test Conference
Volume2015-February
ISSN (Print)1089-3539

Other

Other45th IEEE International Test Conference, ITC 2014
CountryUnited States
CitySeattle
Period14-10-2114-10-23

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

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