TY - GEN
T1 - Regularity-aware routability-driven placement prototyping algorithm for hierarchical mixed-size circuits
AU - Lin, Jai Ming
AU - Yu, Bo Heng
AU - Chang, Li Yen
N1 - Publisher Copyright:
© 2017 IEEE.
Copyright:
Copyright 2017 Elsevier B.V., All rights reserved.
PY - 2017/2/16
Y1 - 2017/2/16
N2 - The paper introduces a routability-driven placement prototyping algorithm for hierarchical mixed-size circuits and pays special attention to regular placement of macros. The three-stage algorithm has become the most popular placement approach for commercial design flows, where placement prototyping plays a critical role in the algorithm because distribution of cells and macros is mainly determined by it. SOC circuits usually contain sets of macros which have identical shapes and are in similar hierarchies. If these macros can be placed regularity, powerplanning will become easier and better routability may be obtained. To consider placement regularity, the paper proposes a physical aware clustering algorithm which is possible to cluster two objects with large area. Experimental results have demonstrated effectiveness of our methodology according to industrial benchmarks tested by a real design flow.
AB - The paper introduces a routability-driven placement prototyping algorithm for hierarchical mixed-size circuits and pays special attention to regular placement of macros. The three-stage algorithm has become the most popular placement approach for commercial design flows, where placement prototyping plays a critical role in the algorithm because distribution of cells and macros is mainly determined by it. SOC circuits usually contain sets of macros which have identical shapes and are in similar hierarchies. If these macros can be placed regularity, powerplanning will become easier and better routability may be obtained. To consider placement regularity, the paper proposes a physical aware clustering algorithm which is possible to cluster two objects with large area. Experimental results have demonstrated effectiveness of our methodology according to industrial benchmarks tested by a real design flow.
UR - http://www.scopus.com/inward/record.url?scp=85015278603&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85015278603&partnerID=8YFLogxK
U2 - 10.1109/ASPDAC.2017.7858362
DO - 10.1109/ASPDAC.2017.7858362
M3 - Conference contribution
AN - SCOPUS:85015278603
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 438
EP - 443
BT - 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017
Y2 - 16 January 2017 through 19 January 2017
ER -