Resist trimming process using CF4/O2 has been developed for sub-0.1 μm polysilicon gate patterning using conventional 248-nm lithography. This process allows the successful fabrication of 80-nm MOS devices. The trimming step is performed in situ as part of the polysilicon gate etching process. The effects of process parameters on trim-rate, trim-rate-nonuniformity and microloading effect are investigated using design-of-experiment. The trim-rate is affected very significantly by the over-etch percentage and O2 gas flow. Bias voltage is of much importance in the linewidth control and the microloading effect, but less significant on trim-rate. The trim-rate increases with increasing RF source power and reactor pressure but decreases with higher bias voltage, indicating that the trimming process is dominated by the neutral reactant species. An optimized recipe has been developed and is proven to be reproducible. The optimum shrinking rate of resist critical dimension is 1.4 nm/s and the trim-rate-nonuniformity σ is about 1.7% of the average trim-rate. Good sidewall profiles of the resist and polysilicon gate are maintained. Transistors having near 80 nm gate length are fabricated successfully by trimming the photoresist having the developed inspection critical dimension (DICD) at 122.6 nm with σ = 2.7 nm. The final inspection critical dimension (FICD) and the effective channel length (Leff) of the aforementioned transistors are 78.5 nm with σ = 2.1 nm and 79.7 nm with σ = 3.2 nm. Both p-channel and n-channel devices show tight saturation current (Idsat) control with σ less than 5% of the mean value.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Atomic and Molecular Physics, and Optics
- Condensed Matter Physics
- Surfaces, Coatings and Films
- Electrical and Electronic Engineering