Resource-efficient FPGA architecture and implementation of hough transform

Zhong Ho Chen, Alvin W.Y. Su, Ming Ting Sun

Research output: Contribution to journalArticlepeer-review

40 Citations (Scopus)

Abstract

Hough transform is widely used for detecting straight lines in an image, but it involves huge computations. For embedded application, field-programmable gate arrays are one of the most used hardware accelerators to achieve real-time implementation of Hough transform. In this paper, we present a resource-efficient architecture and implementation of Hough transform on an FPGA. The incrementing property of Hough transform is described and used to reduce the resource requirement. In order to facilitate parallelism, we divide the image into blocks and apply the incrementing property to pixels within a block and between blocks. Moreover, the locality of Hough transform is analyzed to reduce the memory access. The proposed architecture is implement on an Altera EP2S180F1508C3 device and can operate at a maximum frequency of 200 MHz. It could compute the Hough transform of 512 × 512 test images with 180 orientations in 2.07-3.16 ms without using many FPGA resources (i.e., one could achieve the performance by adopting a low-cost low-end FPGA).

Original languageEnglish
Article number5961666
Pages (from-to)1419-1428
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume20
Issue number8
DOIs
Publication statusPublished - 2012

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'Resource-efficient FPGA architecture and implementation of hough transform'. Together they form a unique fingerprint.

Cite this