TY - JOUR
T1 - Resource-efficient FPGA architecture and implementation of hough transform
AU - Chen, Zhong Ho
AU - Su, Alvin W.Y.
AU - Sun, Ming Ting
N1 - Funding Information:
Manuscript received December 18, 2010; revised April 07, 2011; accepted June 01, 2011. Date of publication July 25, 2011; date of current version June 14, 2012. This work was supported in part by the National Science Council, Taiwan, under Grant NSC 98-2221-E-006-158-MY3.
PY - 2012
Y1 - 2012
N2 - Hough transform is widely used for detecting straight lines in an image, but it involves huge computations. For embedded application, field-programmable gate arrays are one of the most used hardware accelerators to achieve real-time implementation of Hough transform. In this paper, we present a resource-efficient architecture and implementation of Hough transform on an FPGA. The incrementing property of Hough transform is described and used to reduce the resource requirement. In order to facilitate parallelism, we divide the image into blocks and apply the incrementing property to pixels within a block and between blocks. Moreover, the locality of Hough transform is analyzed to reduce the memory access. The proposed architecture is implement on an Altera EP2S180F1508C3 device and can operate at a maximum frequency of 200 MHz. It could compute the Hough transform of 512 × 512 test images with 180 orientations in 2.07-3.16 ms without using many FPGA resources (i.e., one could achieve the performance by adopting a low-cost low-end FPGA).
AB - Hough transform is widely used for detecting straight lines in an image, but it involves huge computations. For embedded application, field-programmable gate arrays are one of the most used hardware accelerators to achieve real-time implementation of Hough transform. In this paper, we present a resource-efficient architecture and implementation of Hough transform on an FPGA. The incrementing property of Hough transform is described and used to reduce the resource requirement. In order to facilitate parallelism, we divide the image into blocks and apply the incrementing property to pixels within a block and between blocks. Moreover, the locality of Hough transform is analyzed to reduce the memory access. The proposed architecture is implement on an Altera EP2S180F1508C3 device and can operate at a maximum frequency of 200 MHz. It could compute the Hough transform of 512 × 512 test images with 180 orientations in 2.07-3.16 ms without using many FPGA resources (i.e., one could achieve the performance by adopting a low-cost low-end FPGA).
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U2 - 10.1109/TVLSI.2011.2160002
DO - 10.1109/TVLSI.2011.2160002
M3 - Article
AN - SCOPUS:84862698573
SN - 1063-8210
VL - 20
SP - 1419
EP - 1428
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 8
M1 - 5961666
ER -