Revisited parasitic bipolar effect in FDSOI MOSFETs: Mechanism, gain extraction and circuit applications

G. Q. Wang, F. Y. Liu, B. Li, J. J. Luo, Y. Huang, X. H. Su, Y. C. Wang, Z. S. Han, C. N. Wu, J. M. Zhang, S. Cristoloveanu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The parasitic bipolar effect in fully-depleted (FD) silicon-on-insulator (SOI) transistors is revisited including impact ionization and band-to-band tunneling. The current gain β of the parasitic bipolar transistor (PBT) was measured at different temperatures and drain voltages. Back-gate biasing was demonstrated to efficiently suppress the bipolar amplification. TCAD simulations showed that the parasitic bipolar effect enhanced the leakage power in circuits. A strategy to counter its effect is proposed based on the power analysis of 6T SRAM cell with back-gate modulation.

Original languageEnglish
Title of host publication2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728187655
DOIs
Publication statusPublished - 2020 Sep 1
Event2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020 - Caen, France
Duration: 2020 Sep 12020 Sep 30

Publication series

Name2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020

Conference

Conference2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2020
Country/TerritoryFrance
CityCaen
Period20-09-0120-09-30

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Instrumentation

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