TY - JOUR
T1 - Routability-driven tsv-Aware floorplanning methodology for fixed-outline 3-d ics
AU - Lin, Jai Ming
AU - Yang, Jung An
N1 - Funding Information:
Manuscript received October 3, 2016; revised December 15, 2016, February 7, 2017, and March 28, 2017; accepted April 5, 2017. Date of publication April 19, 2017; date of current version October 18, 2017. This work was supported by MOST of Taiwan under Grant 105-2221-E-006-245. This paper was recommended by Associate Editor C. C.-N. Chu. (Corresponding author: Jai-Ming Lin.) The authors are with the Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan (e-mail: jmlin@ee.ncku.edu.tw; rogerjan918@gmail.com).
Publisher Copyright:
© 1982-2012 IEEE.
PY - 2017/11
Y1 - 2017/11
N2 - Although 3-D floorplanning has been studied widely, routability which is a very important issue in modern integrated circuit (IC) designs is rarely discussed. Floorplanning in 3-D ICs is much difficult than that in 2-D ICs because of large difference in sizes between modules and through silicon vias (TSVs), which are key components in 3-D ICs. And the locations of TSVs have great impact on wirelength and routability in resulting floorplans. Hence, this paper proposes a TSV-Aware 3-D floorplanning methodology which can consider wirelength and routability at the same time under the fixed-outline constraint. Unlike most of previous works which completely apply the simulated annealing algorithm, our methodology mainly apply deterministic algorithms to resolve the problem. Thus, our approach is more efficient and flexible than previous works. Experimental results have demonstrated that the proposed methodology can significantly reduce routing congestion in 3-D ICs with a slight increase in wirelength.
AB - Although 3-D floorplanning has been studied widely, routability which is a very important issue in modern integrated circuit (IC) designs is rarely discussed. Floorplanning in 3-D ICs is much difficult than that in 2-D ICs because of large difference in sizes between modules and through silicon vias (TSVs), which are key components in 3-D ICs. And the locations of TSVs have great impact on wirelength and routability in resulting floorplans. Hence, this paper proposes a TSV-Aware 3-D floorplanning methodology which can consider wirelength and routability at the same time under the fixed-outline constraint. Unlike most of previous works which completely apply the simulated annealing algorithm, our methodology mainly apply deterministic algorithms to resolve the problem. Thus, our approach is more efficient and flexible than previous works. Experimental results have demonstrated that the proposed methodology can significantly reduce routing congestion in 3-D ICs with a slight increase in wirelength.
UR - http://www.scopus.com/inward/record.url?scp=85037034895&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85037034895&partnerID=8YFLogxK
U2 - 10.1109/TCAD.2017.2695900
DO - 10.1109/TCAD.2017.2695900
M3 - Article
AN - SCOPUS:85037034895
VL - 36
SP - 1856
EP - 1868
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SN - 0278-0070
IS - 11
M1 - 7904617
ER -