Routing-efficient implementation of an internal-response-based BIST architecture

Wei Cheng Lien, Tong Yu Hsieh, Kuen-Jong Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

Recently internal-response-based BIST techniques are proposed. By using internal circuit responses to directly generate test patterns, these techniques can significantly reduce or even eliminate storage requirement for test data. For these techniques, appropriate routing of the circuit internal nets to the BIST circuitry is crucial for minimizing the required area overhead and the induced performance impact. In this paper, an efficient net sharing algorithm together with special response decompressor hardware is proposed to minimize the total number of required internal nets for an internal-response-based BIST scheme. Experimental results show that on average 3.24% of nets and 2.83% area overhead of the response decompressors are sufficient to achieve complete fault coverage for ISCAS'85 circuits.

Original languageEnglish
Title of host publication2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs
Publication statusPublished - 2012 Jul 25
Event2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, Taiwan
Duration: 2012 Apr 232012 Apr 25

Publication series

Name2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

Other

Other2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
CountryTaiwan
CityHsinchu
Period12-04-2312-04-25

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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