RRAM-based neuromorphic hardware reliability improvement by self-healing and error correction

Jia Yun Hu, Kuan Wei Hou, Chih Yen Lo, Yung Fa Chou, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Neural network (NN) has been considered as an important factor for the success of many AI applications. As the von Neumann architecture is inefficient for NN computation, researchers have been investigating new semiconductor devices and architectures for neuromorphic computing. The crossbar RRAM, which is an emerging non-volatile memory composed of memristor devices, can be used to accelerate or emulate the NN computation. However, the memristor device defects exposed during manufacturing or field use may cause performance degradation in the NN, causing reliability issues to the neuromorphic hardware. In this paper, we consider two existing fault models for the 1T1R RRAM cell, i.e., the stuck-at fault and transistor stuck-on fault. Evaluation of their influence to the NN shows that for about 10% faulty cells in the memristor array, the accuracy for the MLP model degrades about 10%, and that for the LeNet 300-100 and LeNet 5 degrades by more than 65%. Therefore, we propose a self-healing and an error correction approach to reduce the accuracy degradation, and improve the reliability (lifetime) of the neuromorphic hardware. Our simulation results show that if we limit the accuracy degradation to within 5%, then the proposed error correction approach for the MLP model will be able to tolerate up to 40% faulty cells, and even up to 60% faulty cells for LeNet 300-100 and LetNet 5 models. Also, the error correction method can extend the lifetime of the neuromorphic hardware by 5% or more.

Original languageEnglish
Title of host publicationProceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages19-24
Number of pages6
ISBN (Print)9781538651803
DOIs
Publication statusPublished - 2018 Sep 11
Event2nd IEEE International Test Conference in Asia, ITC-Asia 2018 - Harbin, China
Duration: 2018 Aug 152018 Aug 17

Publication series

NameProceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018

Other

Other2nd IEEE International Test Conference in Asia, ITC-Asia 2018
CountryChina
CityHarbin
Period18-08-1518-08-17

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality

Fingerprint Dive into the research topics of 'RRAM-based neuromorphic hardware reliability improvement by self-healing and error correction'. Together they form a unique fingerprint.

  • Cite this

    Hu, J. Y., Hou, K. W., Lo, C. Y., Chou, Y. F., & Wu, C. W. (2018). RRAM-based neuromorphic hardware reliability improvement by self-healing and error correction. In Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018 (pp. 19-24). [8462942] (Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ITC-Asia.2018.00014