TY - GEN
T1 - RRAM-based neuromorphic hardware reliability improvement by self-healing and error correction
AU - Hu, Jia Yun
AU - Hou, Kuan Wei
AU - Lo, Chih Yen
AU - Chou, Yung Fa
AU - Wu, Cheng Wen
N1 - Funding Information:
VII. ACKNOWLEDGMENT This work is in part supported by Winbond, R.O.C.
Publisher Copyright:
© 2018 IEEE.
Copyright:
Copyright 2018 Elsevier B.V., All rights reserved.
PY - 2018/9/11
Y1 - 2018/9/11
N2 - Neural network (NN) has been considered as an important factor for the success of many AI applications. As the von Neumann architecture is inefficient for NN computation, researchers have been investigating new semiconductor devices and architectures for neuromorphic computing. The crossbar RRAM, which is an emerging non-volatile memory composed of memristor devices, can be used to accelerate or emulate the NN computation. However, the memristor device defects exposed during manufacturing or field use may cause performance degradation in the NN, causing reliability issues to the neuromorphic hardware. In this paper, we consider two existing fault models for the 1T1R RRAM cell, i.e., the stuck-at fault and transistor stuck-on fault. Evaluation of their influence to the NN shows that for about 10% faulty cells in the memristor array, the accuracy for the MLP model degrades about 10%, and that for the LeNet 300-100 and LeNet 5 degrades by more than 65%. Therefore, we propose a self-healing and an error correction approach to reduce the accuracy degradation, and improve the reliability (lifetime) of the neuromorphic hardware. Our simulation results show that if we limit the accuracy degradation to within 5%, then the proposed error correction approach for the MLP model will be able to tolerate up to 40% faulty cells, and even up to 60% faulty cells for LeNet 300-100 and LetNet 5 models. Also, the error correction method can extend the lifetime of the neuromorphic hardware by 5% or more.
AB - Neural network (NN) has been considered as an important factor for the success of many AI applications. As the von Neumann architecture is inefficient for NN computation, researchers have been investigating new semiconductor devices and architectures for neuromorphic computing. The crossbar RRAM, which is an emerging non-volatile memory composed of memristor devices, can be used to accelerate or emulate the NN computation. However, the memristor device defects exposed during manufacturing or field use may cause performance degradation in the NN, causing reliability issues to the neuromorphic hardware. In this paper, we consider two existing fault models for the 1T1R RRAM cell, i.e., the stuck-at fault and transistor stuck-on fault. Evaluation of their influence to the NN shows that for about 10% faulty cells in the memristor array, the accuracy for the MLP model degrades about 10%, and that for the LeNet 300-100 and LeNet 5 degrades by more than 65%. Therefore, we propose a self-healing and an error correction approach to reduce the accuracy degradation, and improve the reliability (lifetime) of the neuromorphic hardware. Our simulation results show that if we limit the accuracy degradation to within 5%, then the proposed error correction approach for the MLP model will be able to tolerate up to 40% faulty cells, and even up to 60% faulty cells for LeNet 300-100 and LetNet 5 models. Also, the error correction method can extend the lifetime of the neuromorphic hardware by 5% or more.
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U2 - 10.1109/ITC-Asia.2018.00014
DO - 10.1109/ITC-Asia.2018.00014
M3 - Conference contribution
AN - SCOPUS:85054504543
SN - 9781538651803
T3 - Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018
SP - 19
EP - 24
BT - Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018
Y2 - 15 August 2018 through 17 August 2018
ER -