TY - GEN
T1 - S-shaped gate-all-around MOSFETs for high density design
AU - Huang, Ya Chi
AU - Wang, Shui Jinn
AU - Chiang, Meng Hsueh
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/6/29
Y1 - 2017/6/29
N2 - For maximum utilization of layout area using the vertical gate-all-around (VGAA) MOSFETs, this paper proposes a new S-shaped GAA (SGAA) MOSFET structure for 3D integration. The proposed approach improves the layout density per unit cell to extend Moore's Law without the need of aggressive technology scaling. By adjusting the dimensional parameters in the layout schematic, we can tune the device performance such as drive current easily, thus providing a circuit design flexibility for SoC application. Using the same effective channel width for comparison with others vertical GAA structures, the proposed one gives an advantage in better short-channel effects based on three-dimensional TCAD simulation. In addition, by interlacing SGAAs in a repeated unit cell configuration for high density design, just like multi-finger layout, the area density is increased by 3.3× as compared with the ring-shaped GAA MOSFET.
AB - For maximum utilization of layout area using the vertical gate-all-around (VGAA) MOSFETs, this paper proposes a new S-shaped GAA (SGAA) MOSFET structure for 3D integration. The proposed approach improves the layout density per unit cell to extend Moore's Law without the need of aggressive technology scaling. By adjusting the dimensional parameters in the layout schematic, we can tune the device performance such as drive current easily, thus providing a circuit design flexibility for SoC application. Using the same effective channel width for comparison with others vertical GAA structures, the proposed one gives an advantage in better short-channel effects based on three-dimensional TCAD simulation. In addition, by interlacing SGAAs in a repeated unit cell configuration for high density design, just like multi-finger layout, the area density is increased by 3.3× as compared with the ring-shaped GAA MOSFET.
UR - http://www.scopus.com/inward/record.url?scp=85026738277&partnerID=8YFLogxK
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U2 - 10.1109/ULIS.2017.7962566
DO - 10.1109/ULIS.2017.7962566
M3 - Conference contribution
AN - SCOPUS:85026738277
T3 - Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings
SP - 160
EP - 163
BT - Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings
A2 - Nassiopoulou, Androula G.
A2 - Sarafis, Panagiotis
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017
Y2 - 3 April 2017 through 5 April 2017
ER -