S-shaped gate-all-around MOSFETs for high density design

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

For maximum utilization of layout area using the vertical gate-all-around (VGAA) MOSFETs, this paper proposes a new S-shaped GAA (SGAA) MOSFET structure for 3D integration. The proposed approach improves the layout density per unit cell to extend Moore's Law without the need of aggressive technology scaling. By adjusting the dimensional parameters in the layout schematic, we can tune the device performance such as drive current easily, thus providing a circuit design flexibility for SoC application. Using the same effective channel width for comparison with others vertical GAA structures, the proposed one gives an advantage in better short-channel effects based on three-dimensional TCAD simulation. In addition, by interlacing SGAAs in a repeated unit cell configuration for high density design, just like multi-finger layout, the area density is increased by 3.3× as compared with the ring-shaped GAA MOSFET.

Original languageEnglish
Title of host publicationJoint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings
EditorsAndroula G. Nassiopoulou, Panagiotis Sarafis
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages160-163
Number of pages4
ISBN (Electronic)9781509053131
DOIs
Publication statusPublished - 2017 Jun 29
Event2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Athens, Greece
Duration: 2017 Apr 32017 Apr 5

Publication series

NameJoint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings

Other

Other2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017
CountryGreece
CityAthens
Period17-04-0317-04-05

Fingerprint

layouts
field effect transistors
Schematic diagrams
systems-on-a-chip
Networks (circuits)
circuit diagrams
cells
flexibility
adjusting
scaling
rings
configurations
simulation
System-on-chip
thiazole-4-carboxamide adenine dinucleotide

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Instrumentation
  • Electrical and Electronic Engineering

Cite this

Huang, Y. C., Wang, S-J., & Chiang, M-H. (2017). S-shaped gate-all-around MOSFETs for high density design. In A. G. Nassiopoulou, & P. Sarafis (Eds.), Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings (pp. 160-163). [7962566] (Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ULIS.2017.7962566
Huang, Ya Chi ; Wang, Shui-Jinn ; Chiang, Meng-Hsueh. / S-shaped gate-all-around MOSFETs for high density design. Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. editor / Androula G. Nassiopoulou ; Panagiotis Sarafis. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 160-163 (Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings).
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abstract = "For maximum utilization of layout area using the vertical gate-all-around (VGAA) MOSFETs, this paper proposes a new S-shaped GAA (SGAA) MOSFET structure for 3D integration. The proposed approach improves the layout density per unit cell to extend Moore's Law without the need of aggressive technology scaling. By adjusting the dimensional parameters in the layout schematic, we can tune the device performance such as drive current easily, thus providing a circuit design flexibility for SoC application. Using the same effective channel width for comparison with others vertical GAA structures, the proposed one gives an advantage in better short-channel effects based on three-dimensional TCAD simulation. In addition, by interlacing SGAAs in a repeated unit cell configuration for high density design, just like multi-finger layout, the area density is increased by 3.3× as compared with the ring-shaped GAA MOSFET.",
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Huang, YC, Wang, S-J & Chiang, M-H 2017, S-shaped gate-all-around MOSFETs for high density design. in AG Nassiopoulou & P Sarafis (eds), Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings., 7962566, Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 160-163, 2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017, Athens, Greece, 17-04-03. https://doi.org/10.1109/ULIS.2017.7962566

S-shaped gate-all-around MOSFETs for high density design. / Huang, Ya Chi; Wang, Shui-Jinn; Chiang, Meng-Hsueh.

Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. ed. / Androula G. Nassiopoulou; Panagiotis Sarafis. Institute of Electrical and Electronics Engineers Inc., 2017. p. 160-163 7962566 (Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Huang YC, Wang S-J, Chiang M-H. S-shaped gate-all-around MOSFETs for high density design. In Nassiopoulou AG, Sarafis P, editors, Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. p. 160-163. 7962566. (Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings). https://doi.org/10.1109/ULIS.2017.7962566