Scalable security processor design and its implementation

Chen Hsing Wang, Jen Chieh Yeh, Chih Tsun Huang, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)


This paper presents a security processor to accelerate cryptographic processing in modern security applications. Our security processor is capable of popular cryptographic functions such as RSA, AES, hashing and random number generation, etc. With proposed Crypto-DMA controller, data gathering and scattering become flexible for security processing, using a simple descriptor-based programming model. The architecture of the security processor with its core-based platform is scalable and configurable for security variations in performance, cost and power consumption. Different number of data channels and crypto-engines can be used to meet the specifications. In addition, a DFT (design for test) platform is also implemented for the design-test integration. The security processor has been fabricated (using UMC 0.18μm CMOS technology) and measured. The core area is 3.899mm × 2.296mm (525K gates approximately) and the operating clock rate is 66MHz.

Original languageEnglish
Title of host publication2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
PublisherIEEE Computer Society
Number of pages4
ISBN (Print)0780391624, 9780780391628
Publication statusPublished - 2006 Dec 1
Event1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005 - Hsinchu, Taiwan
Duration: 2005 Nov 12005 Nov 3

Publication series

Name2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005


Other1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials


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