Scaling study of nanowire and multi-gate MOSFETs

Chin Yu Chen, Yi Bo Liao, Meng-Hsueh Chiang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

In this paper, comprehensive comparisons of nanowire and multi-gate nMOSFETs in scaling capability using three-dimensional numerical simulations are presented. Their short channel effects and device performances are also investigated. The nanowire device requires less device dimension constraint on body diameter due to perfect surrounding gate-to-gate capacitive coupling and hence it is promising at sub-45 nm node.

Original languageEnglish
Title of host publicationICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings
Pages57-60
Number of pages4
DOIs
Publication statusPublished - 2008 Dec 1
Event2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008 - Beijing, China
Duration: 2008 Oct 202008 Oct 23

Publication series

NameInternational Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Other

Other2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008
CountryChina
CityBeijing
Period08-10-2008-10-23

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Condensed Matter Physics
  • Electronic, Optical and Magnetic Materials

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