Scaling study of nanowire and multi-gate MOSFETs

Chin Yu Chen; Yi Bo Liao; Meng-Hsueh Chiang

doi:10.1109/ICSICT.2008.4734462

Scaling study of nanowire and multi-gate MOSFETs

Chin Yu Chen
, Yi Bo Liao
, Meng-Hsueh Chiang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

In this paper, comprehensive comparisons of nanowire and multi-gate nMOSFETs in scaling capability using three-dimensional numerical simulations are presented. Their short channel effects and device performances are also investigated. The nanowire device requires less device dimension constraint on body diameter due to perfect surrounding gate-to-gate capacitive coupling and hence it is promising at sub-45 nm node.

Original language	English
Title of host publication	ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings
Pages	57-60
Number of pages	4
DOIs	https://doi.org/10.1109/ICSICT.2008.4734462
Publication status	Published - 2008 Dec 1
Event	2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008 - Beijing, China Duration: 2008 Oct 20 → 2008 Oct 23

Publication series

Name	International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Other

Other	2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008
Country/Territory	China
City	Beijing
Period	08-10-20 → 08-10-23

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Condensed Matter Physics
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ICSICT.2008.4734462

Cite this

Chen, C. Y., Liao, Y. B., & Chiang, M.-H. (2008). Scaling study of nanowire and multi-gate MOSFETs. In ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings (pp. 57-60). Article 4734462 (International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT). https://doi.org/10.1109/ICSICT.2008.4734462

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title = "Scaling study of nanowire and multi-gate MOSFETs",

abstract = "In this paper, comprehensive comparisons of nanowire and multi-gate nMOSFETs in scaling capability using three-dimensional numerical simulations are presented. Their short channel effects and device performances are also investigated. The nanowire device requires less device dimension constraint on body diameter due to perfect surrounding gate-to-gate capacitive coupling and hence it is promising at sub-45 nm node.",

author = "Chen, \{Chin Yu\} and Liao, \{Yi Bo\} and Meng-Hsueh Chiang",

year = "2008",

month = dec,

day = "1",

doi = "10.1109/ICSICT.2008.4734462",

language = "English",

isbn = "9781424421855",

series = "International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT",

pages = "57--60",

booktitle = "ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings",

note = "2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008 ; Conference date: 20-10-2008 Through 23-10-2008",

}

Chen, CY, Liao, YB & Chiang, M-H 2008, Scaling study of nanowire and multi-gate MOSFETs. in ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings., 4734462, International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT, pp. 57-60, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008, Beijing, China, 08-10-20. https://doi.org/10.1109/ICSICT.2008.4734462

Scaling study of nanowire and multi-gate MOSFETs. / Chen, Chin Yu; Liao, Yi Bo; Chiang, Meng-Hsueh.
ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings. 2008. p. 57-60 4734462 (International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Liao, Yi Bo

AU - Chiang, Meng-Hsueh

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N2 - In this paper, comprehensive comparisons of nanowire and multi-gate nMOSFETs in scaling capability using three-dimensional numerical simulations are presented. Their short channel effects and device performances are also investigated. The nanowire device requires less device dimension constraint on body diameter due to perfect surrounding gate-to-gate capacitive coupling and hence it is promising at sub-45 nm node.

AB - In this paper, comprehensive comparisons of nanowire and multi-gate nMOSFETs in scaling capability using three-dimensional numerical simulations are presented. Their short channel effects and device performances are also investigated. The nanowire device requires less device dimension constraint on body diameter due to perfect surrounding gate-to-gate capacitive coupling and hence it is promising at sub-45 nm node.

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DO - 10.1109/ICSICT.2008.4734462

M3 - Conference contribution

AN - SCOPUS:60649088932

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T3 - International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

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BT - ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings

T2 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008

Y2 - 20 October 2008 through 23 October 2008

ER -

Scaling study of nanowire and multi-gate MOSFETs

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All Science Journal Classification (ASJC) codes

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