TY - GEN
T1 - Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks
AU - Chen, Yan Fu
AU - Kang, Duo Yao
AU - Lee, Kuen Jong
N1 - Funding Information:
ACKNOWLEDGMENT This work is supported in part by the Ministry of Science and Technology of Taiwan under Contract 109-2218-E-006-025.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - A scan-based test chip architecture composed of a two-dimensional array of C-testable blocks (CTBs) and scan registers is proposed, where each CTB contains several XOR modules and has the distinguished VH-bijection property, i.e., each CTB is bijective, and any change in either the vertical or horizontal input of a CTB will lead to changes in both vertical and horizontal outputs. We present a novel method to systematically embed each combinational standard cell in a cell library to an XOR module such that almost all input pattern faults (including all stuck-at faults) in the standard cells can be detected even if multiple faults exist. Great diagnosability is achieved due to the VH-bijection property of CTBs, the full fault coverage property for faults in the standard cells inside CTBs, and the scan-based test chip architecture.
AB - A scan-based test chip architecture composed of a two-dimensional array of C-testable blocks (CTBs) and scan registers is proposed, where each CTB contains several XOR modules and has the distinguished VH-bijection property, i.e., each CTB is bijective, and any change in either the vertical or horizontal input of a CTB will lead to changes in both vertical and horizontal outputs. We present a novel method to systematically embed each combinational standard cell in a cell library to an XOR module such that almost all input pattern faults (including all stuck-at faults) in the standard cells can be detected even if multiple faults exist. Great diagnosability is achieved due to the VH-bijection property of CTBs, the full fault coverage property for faults in the standard cells inside CTBs, and the scan-based test chip architecture.
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U2 - 10.1109/ITC50671.2022.00015
DO - 10.1109/ITC50671.2022.00015
M3 - Conference contribution
AN - SCOPUS:85146151461
T3 - Proceedings - International Test Conference
SP - 82
EP - 91
BT - Proceedings - 2022 IEEE International Test Conference, ITC 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE International Test Conference, ITC 2022
Y2 - 23 September 2022 through 30 September 2022
ER -