Scan design for asynchronous sequential logic circuits using SR-latches

Ming-Der Shieh, Chin Long Wey, P. David Fisher

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

This paper presents a scan design for asynchronous sequential logic circuits (ASLCs) using modified SR-latches. With this scan structure, an ASLC is operated in an asynchronous way during the normal operation mode, while it is synchronized with clock signals during the test mode. The modified SR-latch is free of hazards and races for both fault-free and faulty circuits and the scan structure is race-free during normal operation and test modes. The structure achieves full testability of all single stuck-at faults.

Original languageEnglish
Title of host publicationMidwest Symposium on Circuits and Systems
PublisherPubl by IEEE
Pages1300-1303
Number of pages4
ISBN (Print)0780317610
Publication statusPublished - 1993 Dec 1
EventProceedings of the 36th Midwest Symposium on Circuits and Systems - Detroit, MI, USA
Duration: 1993 Aug 161993 Aug 18

Publication series

NameMidwest Symposium on Circuits and Systems
Volume2

Other

OtherProceedings of the 36th Midwest Symposium on Circuits and Systems
CityDetroit, MI, USA
Period93-08-1693-08-18

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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