In a high-performance superscalar processor, the instruction scheduler often comes with poor scalability and high complexity due to the expensive instruction wakeup operation. Using detailed simulation-based analyses, we find that the wakeup distances between two dependent instructions are short. By exploiting this wakeup locality, an effective wakeup design is proposed to improve the speed, power, and scalability of the dynamic scheduler. By limiting the wakeup range of instructions, load capacitance and match activities on the scheduler's critical path can be reduced. The architectural level simulation and circuit-level timing analyses show that the proposed design saves 65-76% of the power consumption, reduces 44-78% in the wakeup latency with negligible (less than 1%) performance degradation. The results also show that the proposed design is excellent in scalability.