SDRAM delay fault modeling and performance testing

Yu Tsao Hsing, Chun Chieh Huang, Jen Chieh Yeh, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

DRAM timing parameter testing has always been considered a time-consuming process. This paper presents a systematic approach to analysis and classification of the synchronous DRAM (SDRAM) delay failure modes. Four delay fault models with March expression are proposed to cover important DRAM timing parameters. By at-speed March testing of these four types of delay faults, we can verify the DRAM timing specifications.

Original languageEnglish
Title of host publicationProceedings - 25th IEEE VLSI Test Symposium, VTS'07
Pages53-58
Number of pages6
DOIs
Publication statusPublished - 2007 Dec 1
Event25th IEEE VLSI Test Symposium, VTS'07 - Berkeley, CA, United States
Duration: 2007 May 62007 May 10

Publication series

NameProceedings of the IEEE VLSI Test Symposium

Conference

Conference25th IEEE VLSI Test Symposium, VTS'07
CountryUnited States
CityBerkeley, CA
Period07-05-0607-05-10

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

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