Abstract
The configurations and adjusting method of a subrange analog-to-digital converter (ADC) are provided. The provided subrange ADC includes a X.5-bit flash ADC, a Y-bit SAR ADC and a (X+Y)-bit segmented capacitive digital-to-analog converter (DAC).
| Translated title of the contribution | 分段式類比數位轉換器及其方法 |
|---|---|
| Original language | English |
| Patent number | 8310388 |
| Publication status | Published - 2012 Jun 21 |