Selection of high-order analog response extractor for Σ-Δ modulation based analog built-in self-test applications

Hao Chiao Hong, Cheng Wen Wu

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)

Abstract

The analog built-in self-test (BIST) scheme using a single-bit second-order Σ-Δ modulator as the analog response extractor (ARE) has been proven to be a low-cost solution. For applications where higher resolution or wider bandwidth is required, a higher-order Σ-Δ modulator may be more suitable, since it allows a reduced oversampling ratio (OSR) for a given resolution. The ARE candidates also need to operate at a reasonable range of OSR and tolerate circuit imperfection to serve different test requirements. Two single-loop and two cascaded single-bit fifth-order Σ-Δ modulators are compared. They are digitally testable with the proposed low-cost design-for-testability circuit. The high-order Σ-Δ modulator, a cascade of the second-order and first-order ones, is considered as the best choice for OSR ≥ 16 because of its small hardware overhead, lower sensitivity to the circuit imperfections, unconditional stability, and high flexibility in adjusting to a wide range of OSR. This is verified by simulation results.

Original languageEnglish
Pages (from-to)103-115
Number of pages13
JournalJournal of the Chinese Institute of Electrical Engineering, Transactions of the Chinese Institute of Engineers, Series E/Chung KuoTien Chi Kung Chieng Hsueh K'an
Volume11
Issue number2
Publication statusPublished - 2004 May 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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