Selectively multiple-valued memory design using negative differential resistance circuits implemented by standard SiGe BiCMOS process

Dong Shang Liang; Cheng Chi Tai; Kwang Jow Gan; Yi Zhi Lin

doi:10.1109/ICCCAS.2008.4657954

Selectively multiple-valued memory design using negative differential resistance circuits implemented by standard SiGe BiCMOS process

Dong Shang Liang, Cheng Chi Tai, Kwang Jow Gan, Yi Zhi Lin

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A novel multiple-valued memory circuit design using negative differential resistance (NDR) circuit based on standard 0.35μm SiGe process is demonstrated. The NDR circuit is made of metal-oxide-semiconductor field-effect-transistor (MOS) and heterojunction-bipolar-transistor (DBT) devices, but it can show the NDR characteristic in its current-voltage curve by suitably designing the MOS widths/lengths parameters. The memory circuit use three-peak MOS-HBT-NDR circuit as the driver and three constant current sources as the load. During suitably controlling the current sources on and off, we can obtain a sequence of multiple-valued logic output.

Original language	English
Title of host publication	2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008
Pages	1075-1078
Number of pages	4
DOIs	https://doi.org/10.1109/ICCCAS.2008.4657954
Publication status	Published - 2008
Event	2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008 - Xiamen, Fujian Province, China Duration: 2008 May 25 → 2008 May 27

Publication series

Name	2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008

Other

Other	2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008
Country/Territory	China
City	Xiamen, Fujian Province
Period	08-05-25 → 08-05-27

All Science Journal Classification (ASJC) codes

Computer Networks and Communications
Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/ICCCAS.2008.4657954

Cite this

Liang, D. S., Tai, C. C., Gan, K. J., & Lin, Y. Z. (2008). Selectively multiple-valued memory design using negative differential resistance circuits implemented by standard SiGe BiCMOS process. In 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008 (pp. 1075-1078). Article 4657954 (2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008). https://doi.org/10.1109/ICCCAS.2008.4657954

Liang, Dong Shang ; Tai, Cheng Chi ; Gan, Kwang Jow et al. / Selectively multiple-valued memory design using negative differential resistance circuits implemented by standard SiGe BiCMOS process. 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008. 2008. pp. 1075-1078 (2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008).

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title = "Selectively multiple-valued memory design using negative differential resistance circuits implemented by standard SiGe BiCMOS process",

abstract = "A novel multiple-valued memory circuit design using negative differential resistance (NDR) circuit based on standard 0.35μm SiGe process is demonstrated. The NDR circuit is made of metal-oxide-semiconductor field-effect-transistor (MOS) and heterojunction-bipolar-transistor (DBT) devices, but it can show the NDR characteristic in its current-voltage curve by suitably designing the MOS widths/lengths parameters. The memory circuit use three-peak MOS-HBT-NDR circuit as the driver and three constant current sources as the load. During suitably controlling the current sources on and off, we can obtain a sequence of multiple-valued logic output.",

author = "Liang, {Dong Shang} and Tai, {Cheng Chi} and Gan, {Kwang Jow} and Lin, {Yi Zhi}",

year = "2008",

doi = "10.1109/ICCCAS.2008.4657954",

language = "English",

isbn = "9781424420636",

series = "2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008",

pages = "1075--1078",

booktitle = "2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008",

note = "2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008 ; Conference date: 25-05-2008 Through 27-05-2008",

}

Liang, DS, Tai, CC, Gan, KJ & Lin, YZ 2008, Selectively multiple-valued memory design using negative differential resistance circuits implemented by standard SiGe BiCMOS process. in 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008., 4657954, 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008, pp. 1075-1078, 2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008, Xiamen, Fujian Province, China, 08-05-25. https://doi.org/10.1109/ICCCAS.2008.4657954

Selectively multiple-valued memory design using negative differential resistance circuits implemented by standard SiGe BiCMOS process. / Liang, Dong Shang; Tai, Cheng Chi; Gan, Kwang Jow et al.
2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008. 2008. p. 1075-1078 4657954 (2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Selectively multiple-valued memory design using negative differential resistance circuits implemented by standard SiGe BiCMOS process

AU - Liang, Dong Shang

AU - Tai, Cheng Chi

AU - Gan, Kwang Jow

AU - Lin, Yi Zhi

PY - 2008

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N2 - A novel multiple-valued memory circuit design using negative differential resistance (NDR) circuit based on standard 0.35μm SiGe process is demonstrated. The NDR circuit is made of metal-oxide-semiconductor field-effect-transistor (MOS) and heterojunction-bipolar-transistor (DBT) devices, but it can show the NDR characteristic in its current-voltage curve by suitably designing the MOS widths/lengths parameters. The memory circuit use three-peak MOS-HBT-NDR circuit as the driver and three constant current sources as the load. During suitably controlling the current sources on and off, we can obtain a sequence of multiple-valued logic output.

AB - A novel multiple-valued memory circuit design using negative differential resistance (NDR) circuit based on standard 0.35μm SiGe process is demonstrated. The NDR circuit is made of metal-oxide-semiconductor field-effect-transistor (MOS) and heterojunction-bipolar-transistor (DBT) devices, but it can show the NDR characteristic in its current-voltage curve by suitably designing the MOS widths/lengths parameters. The memory circuit use three-peak MOS-HBT-NDR circuit as the driver and three constant current sources as the load. During suitably controlling the current sources on and off, we can obtain a sequence of multiple-valued logic output.

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T3 - 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008

SP - 1075

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BT - 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008

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Y2 - 25 May 2008 through 27 May 2008

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Liang DS, Tai CC, Gan KJ, Lin YZ. Selectively multiple-valued memory design using negative differential resistance circuits implemented by standard SiGe BiCMOS process. In 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008. 2008. p. 1075-1078. 4657954. (2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008). doi: 10.1109/ICCCAS.2008.4657954

Selectively multiple-valued memory design using negative differential resistance circuits implemented by standard SiGe BiCMOS process

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