Selectively multiple-valued memory design using negative differential resistance circuits implemented by standard SiGe BiCMOS process

Dong Shang Liang, Cheng Chi Tai, Kwang Jow Gan, Yi Zhi Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A novel multiple-valued memory circuit design using negative differential resistance (NDR) circuit based on standard 0.35μm SiGe process is demonstrated. The NDR circuit is made of metal-oxide-semiconductor field-effect-transistor (MOS) and heterojunction-bipolar-transistor (DBT) devices, but it can show the NDR characteristic in its current-voltage curve by suitably designing the MOS widths/lengths parameters. The memory circuit use three-peak MOS-HBT-NDR circuit as the driver and three constant current sources as the load. During suitably controlling the current sources on and off, we can obtain a sequence of multiple-valued logic output.

Original languageEnglish
Title of host publication2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008
Pages1075-1078
Number of pages4
DOIs
Publication statusPublished - 2008 Dec 1
Event2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008 - Xiamen, Fujian Province, China
Duration: 2008 May 252008 May 27

Publication series

Name2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008

Other

Other2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008
CountryChina
CityXiamen, Fujian Province
Period08-05-2508-05-27

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Selectively multiple-valued memory design using negative differential resistance circuits implemented by standard SiGe BiCMOS process'. Together they form a unique fingerprint.

  • Cite this

    Liang, D. S., Tai, C. C., Gan, K. J., & Lin, Y. Z. (2008). Selectively multiple-valued memory design using negative differential resistance circuits implemented by standard SiGe BiCMOS process. In 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008 (pp. 1075-1078). [4657954] (2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008). https://doi.org/10.1109/ICCCAS.2008.4657954