Abstract
For NAND flash memory, the feature size scaling will suffer from electrical and reliability challenges. First, as the word line scaling down, the capacitance coupling among unrelated floating gate would increase which leads to Vth shift and widen distribution. Secondary, the required floating gate height should be reduced due to disturb between memories cell [1]. Therefore, the floating gate height by means of self aligned STI (SA-STI) and poly CMP process need to be well controlled or the characteristics of cell function will be critical challenge. Although the technologies of SA-STI and poly CMP both are popular for floating gate (FG) and active area (AA) in NAND flash process for a long time, we would like to show the scaling cell structure and introduce this technology node integration process. This paper describes the characteristics of self-align STI and poly CMP process applying into 70nm node high density NAND flash memories. It should be mentioned that this integrated process is easy to direct shrink to 70nm generation beyond.
Original language | English |
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Pages | 427-431 |
Number of pages | 5 |
Publication status | Published - 2006 |
Event | 23rd International VLSI Multilevel Interconnection Conference, VMIC 2006 - Fremont, CA, United States Duration: 2006 Sept 26 → 2006 Sept 28 |
Conference
Conference | 23rd International VLSI Multilevel Interconnection Conference, VMIC 2006 |
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Country/Territory | United States |
City | Fremont, CA |
Period | 06-09-26 → 06-09-28 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering