Sensorless dead-time exploration for digitally controlled switching converters

Bo Ting Yeh; Chun Hung Yang; Kai Cheung Juang; Chien Hung Tsai

doi:10.1109/VLDI-DAT.2013.6533802

Sensorless dead-time exploration for digitally controlled switching converters

Bo Ting Yeh, Chun Hung Yang, Kai Cheung Juang, Chien Hung Tsai

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

This paper proposes a sensorless dead-time exploration algorithm for a synchronous switching converter. An exploration algorithm using delay-line circuits instead of high frequency circuits is used to accelerate optimal dead-time searching and provide high quantization resolution with the dead-time step. The dead-time controller utilizes the relationship between the duty-cycle command and power loss to find the optimal dead-time without sensing any power-stage signals. This approach is well suited for digital integrated circuit implementation. Experimental results show that the converter, fabricated in the 0.18-μm CMOS process, can quickly find the optimal dead-time and improve efficiency.

Original language	English
Title of host publication	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
DOIs	https://doi.org/10.1109/VLDI-DAT.2013.6533802
Publication status	Published - 2013 Aug 15
Event	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 - Hsinchu, Taiwan Duration: 2013 Apr 22 → 2013 Apr 24

Publication series

Name	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

Other

Other	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
Country/Territory	Taiwan
City	Hsinchu
Period	13-04-22 → 13-04-24

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/VLDI-DAT.2013.6533802

Cite this

Yeh, B. T., Yang, C. H., Juang, K. C., & Tsai, C. H. (2013). Sensorless dead-time exploration for digitally controlled switching converters. In 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 Article 6533802 (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013). https://doi.org/10.1109/VLDI-DAT.2013.6533802

@inproceedings{b1e0b99f32b242e0a6ade971cbcfed0b,

title = "Sensorless dead-time exploration for digitally controlled switching converters",

abstract = "This paper proposes a sensorless dead-time exploration algorithm for a synchronous switching converter. An exploration algorithm using delay-line circuits instead of high frequency circuits is used to accelerate optimal dead-time searching and provide high quantization resolution with the dead-time step. The dead-time controller utilizes the relationship between the duty-cycle command and power loss to find the optimal dead-time without sensing any power-stage signals. This approach is well suited for digital integrated circuit implementation. Experimental results show that the converter, fabricated in the 0.18-μm CMOS process, can quickly find the optimal dead-time and improve efficiency.",

author = "Yeh, {Bo Ting} and Yang, {Chun Hung} and Juang, {Kai Cheung} and Tsai, {Chien Hung}",

year = "2013",

month = aug,

day = "15",

doi = "10.1109/VLDI-DAT.2013.6533802",

language = "English",

isbn = "9781467344357",

series = "2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013",

booktitle = "2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013",

note = "2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 ; Conference date: 22-04-2013 Through 24-04-2013",

}

Yeh, BT, Yang, CH, Juang, KC & Tsai, CH 2013, Sensorless dead-time exploration for digitally controlled switching converters. in 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013., 6533802, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, 13-04-22. https://doi.org/10.1109/VLDI-DAT.2013.6533802

Sensorless dead-time exploration for digitally controlled switching converters. / Yeh, Bo Ting; Yang, Chun Hung; Juang, Kai Cheung et al.
2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 2013. 6533802 (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Sensorless dead-time exploration for digitally controlled switching converters

AU - Yeh, Bo Ting

AU - Yang, Chun Hung

AU - Juang, Kai Cheung

AU - Tsai, Chien Hung

PY - 2013/8/15

Y1 - 2013/8/15

N2 - This paper proposes a sensorless dead-time exploration algorithm for a synchronous switching converter. An exploration algorithm using delay-line circuits instead of high frequency circuits is used to accelerate optimal dead-time searching and provide high quantization resolution with the dead-time step. The dead-time controller utilizes the relationship between the duty-cycle command and power loss to find the optimal dead-time without sensing any power-stage signals. This approach is well suited for digital integrated circuit implementation. Experimental results show that the converter, fabricated in the 0.18-μm CMOS process, can quickly find the optimal dead-time and improve efficiency.

AB - This paper proposes a sensorless dead-time exploration algorithm for a synchronous switching converter. An exploration algorithm using delay-line circuits instead of high frequency circuits is used to accelerate optimal dead-time searching and provide high quantization resolution with the dead-time step. The dead-time controller utilizes the relationship between the duty-cycle command and power loss to find the optimal dead-time without sensing any power-stage signals. This approach is well suited for digital integrated circuit implementation. Experimental results show that the converter, fabricated in the 0.18-μm CMOS process, can quickly find the optimal dead-time and improve efficiency.

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M3 - Conference contribution

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T3 - 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

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T2 - 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

Y2 - 22 April 2013 through 24 April 2013

ER -

Sensorless dead-time exploration for digitally controlled switching converters

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