Sensorless dead-time exploration for digitally controlled switching converters

Bo Ting Yeh, Chun Hung Yang, Kai Cheung Juang, Chien Hung Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper proposes a sensorless dead-time exploration algorithm for a synchronous switching converter. An exploration algorithm using delay-line circuits instead of high frequency circuits is used to accelerate optimal dead-time searching and provide high quantization resolution with the dead-time step. The dead-time controller utilizes the relationship between the duty-cycle command and power loss to find the optimal dead-time without sensing any power-stage signals. This approach is well suited for digital integrated circuit implementation. Experimental results show that the converter, fabricated in the 0.18-μm CMOS process, can quickly find the optimal dead-time and improve efficiency.

Original languageEnglish
Title of host publication2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
DOIs
Publication statusPublished - 2013 Aug 15
Event2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 - Hsinchu, Taiwan
Duration: 2013 Apr 222013 Apr 24

Publication series

Name2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

Other

Other2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
CountryTaiwan
CityHsinchu
Period13-04-2213-04-24

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Yeh, B. T., Yang, C. H., Juang, K. C., & Tsai, C. H. (2013). Sensorless dead-time exploration for digitally controlled switching converters. In 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 [6533802] (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013). https://doi.org/10.1109/VLDI-DAT.2013.6533802