Serial diagnostic fault simulation for synchronous sequential circuits

Shung Chih Chen, Jer-Min Jou

Research output: Contribution to journalArticle

Abstract

In this paper, a time and memory-efficient diagnostic fault simulator for sequential circuits is presented. A two level optimization technique has been developed and used to prompt the processing speed. In the high level, an efficient list, which stores the indistinguishable faults, for each fault during the diagnostic fault simulation, and the list maintaining algorithm are applied. Thus the number of fault-pair output response comparisons among all the faults is minimized. In the low level, a bit-parallel comparison is developed to speed up the comparison process. Therefore, the different diagnostic measure reports for a given test set can be generated very quickly. In addition, the simulator is extended to diagnose the single stuck-at device fault. Experimental results show that this diagnostic fault simulator achieves a significant speedup compared to previous methods.

Original languageEnglish
Pages (from-to)157-170
Number of pages14
JournalIntegration, the VLSI Journal
Volume23
Issue number2
DOIs
Publication statusPublished - 1997 Jan 1

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Sequential circuits
Simulators
Data storage equipment
Processing

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

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Serial diagnostic fault simulation for synchronous sequential circuits. / Chen, Shung Chih; Jou, Jer-Min.

In: Integration, the VLSI Journal, Vol. 23, No. 2, 01.01.1997, p. 157-170.

Research output: Contribution to journalArticle

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