In this paper, a time and memory-efficient diagnostic fault simulator for sequential circuits is presented. A two level optimization technique has been developed and used to prompt the processing speed. In the high level, an efficient list, which stores the indistinguishable faults, for each fault during the diagnostic fault simulation, and the list maintaining algorithm are applied. Thus the number of fault-pair output response comparisons among all the faults is minimized. In the low level, a bit-parallel comparison is developed to speed up the comparison process. Therefore, the different diagnostic measure reports for a given test set can be generated very quickly. In addition, the simulator is extended to diagnose the single stuck-at device fault. Experimental results show that this diagnostic fault simulator achieves a significant speedup compared to previous methods.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering