Serial low power bus coding for VLSI

Chih-Hung Kuo, Wey Bang Wu, Yi Jang Wu, Jia Hung Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

In this paper, we present a serial coding method to reduce the bus transition activity and implement error control code to reduce bit error probability. We propose two kinds of coding method for data bus. The basic principle is to append extra information pattern to the back of the original data packet. Experimental results show that the proposed coding scheme can reduce total bus transitions by 12% on the average, compared to that of the uncoded patterns, without adding redundant bitlines on the bus.

Original languageEnglish
Title of host publication2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings - Circuits and Systems
Pages2449-2453
Number of pages5
DOIs
Publication statusPublished - 2006 Dec 1
Event2006 International Conference on Communications, Circuits and Systems, ICCCAS - Guilin, China
Duration: 2006 Jun 252006 Jun 28

Publication series

Name2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings
Volume4

Other

Other2006 International Conference on Communications, Circuits and Systems, ICCCAS
CountryChina
CityGuilin
Period06-06-2506-06-28

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Kuo, C-H., Wu, W. B., Wu, Y. J., & Lin, J. H. (2006). Serial low power bus coding for VLSI. In 2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings - Circuits and Systems (pp. 2449-2453). [4064418] (2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings; Vol. 4). https://doi.org/10.1109/ICCCAS.2006.285171