Simplified delay design guidelines for on-chip global interconnects

Liang Zhang, Wentai Liu, Rizwan Bashirullah, John Wilson, Paul Franzon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Based on the effective attenuation constant approximation of distributed RLC lines, simplified design guidelines are presented dealing with the line characteristics, termination, and delay estimation of on-chip global interconnects. RC delay models are verified to be still accurate for a wide range of parameters conventionally considered inductive. A new closed-form RLC delay formula is developed when RC models are inadequate. The formula works for both voltage and current-mode signaling and exhibits 10% accuracy of SPICE simulation. This work is suitable for global routing topologies and iterative layout optimization.

Original languageEnglish
Title of host publicationProceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004
Subtitle of host publicationVLSI in the Nanometer Era
PublisherAssociation for Computing Machinery (ACM)
Pages29-32
Number of pages4
ISBN (Print)1581138539, 9781581138535
DOIs
Publication statusPublished - 2004
EventProceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era - Boston, MA, United States
Duration: 2004 Apr 262004 Apr 28

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI

Conference

ConferenceProceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era
Country/TerritoryUnited States
CityBoston, MA
Period04-04-2604-04-28

All Science Journal Classification (ASJC) codes

  • General Engineering

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