Simulation and measurements of stray minority carrier protection structures in CMOS image sensors

Recently, the rapid growth of CMOS technology has made it possible to integrate more periphery circuits into a CMOS image sensor. Although these periphery circuits improve image quality, they also lead to the generation of more stray minority carriers. Because the number of stray minority carriers is proportional to the frequency, the affected region increases with increasing operating frequency. Placing an appropriate absorber between the periphery circuits and the pixel has traditionally been accepted as the best solution for this issue. Four protection tactics were simulated in software and verified in a fabricated CMOS image sensor. The imager was fabricated using TSMC 1-poly 6-metal 0.18-μm process technology. On this chip, ten noise sources outside the pixel array were used to verify the effectiveness of the protection tactics in off-array tests, whereas in-pixel noise sources were used in in-pixel tests. To quantify the influence of stray minority carriers in the off-array test, the maximum depth of an affected region (DAR) was measured in a processed binary image. The off-array experimental results revealed that the DAR increased with either an increased operating frequency or a decreased separation between the noise source and the pixel array. The DAR of the affected pixels can be eliminated up to 48.1% and 23.8% by using the N-well and N-diffusion guard rings, respectively. The in-pixel experimental results have shown that the N-diffusion digital pixel implementation reduced the noise by 63.2% while only increasing the area by 10.68%. Detailed information about the effectiveness of different protection tactics in an imager design was collected in this paper. This paper can potentially provide a reference to help imager designers choose an appropriate protection tactic.