Simulation-Based Study of Hybrid Fin/Planar LDMOS Design for FinFET-Based System-on-Chip Technology

Yi Ting Wu; Fei Ding; Daniel Connelly; Peng Zheng; Meng Hsueh Chiang; Jone F. Chen; Tsu Jae King Liu

doi:10.1109/TED.2017.2736442

Simulation-Based Study of Hybrid Fin/Planar LDMOS Design for FinFET-Based System-on-Chip Technology

Yi Ting Wu, Fei Ding, Daniel Connelly, Peng Zheng, Meng Hsueh Chiang, Jone F. Chen, Tsu Jae King Liu

Research output: Contribution to journal › Article › peer-review

24 Citations (Scopus)

Abstract

A hybrid fin/planar lateral double-diffused MOSFET (LDMOS) design (hybrid FET) is proposed for the high-voltage input-output devices in a FinFET-based system-on-chip (SoC) technology. 3-D technology computer-aided design simulations show that a planar drift region and a planar drain region are advantageous for higher breakdown voltage (BV) to specific on-state resistance (R on\ sp) ratio (BV²/ R on\ sp). By slightly extending the planar portion of the semiconductor active region into the gated channel region, the theoretical limit of BV²/ R on\ sp for LDMOS can be surpassed. Hybrid FETs can be fabricated using a process flow that is compatible with the state-of-art FinFET SoC technology.

Original language	English
Article number	8010312
Pages (from-to)	4193-4199
Number of pages	7
Journal	IEEE Transactions on Electron Devices
Volume	64
Issue number	10
DOIs	https://doi.org/10.1109/TED.2017.2736442
Publication status	Published - 2017 Oct

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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title = "Simulation-Based Study of Hybrid Fin/Planar LDMOS Design for FinFET-Based System-on-Chip Technology",

abstract = "A hybrid fin/planar lateral double-diffused MOSFET (LDMOS) design (hybrid FET) is proposed for the high-voltage input-output devices in a FinFET-based system-on-chip (SoC) technology. 3-D technology computer-aided design simulations show that a planar drift region and a planar drain region are advantageous for higher breakdown voltage (BV) to specific on-state resistance (R on\ sp) ratio (BV2/ R on\ sp). By slightly extending the planar portion of the semiconductor active region into the gated channel region, the theoretical limit of BV2/ R on\ sp for LDMOS can be surpassed. Hybrid FETs can be fabricated using a process flow that is compatible with the state-of-art FinFET SoC technology.",

author = "Wu, {Yi Ting} and Fei Ding and Daniel Connelly and Peng Zheng and Chiang, {Meng Hsueh} and Chen, {Jone F.} and Liu, {Tsu Jae King}",

note = "Funding Information: Manuscript received June 15, 2017; revised July 31, 2017; accepted August 2, 2017. Date of publication August 14, 2017; date of current version September 20, 2017. This work was supported by the Ministry of Science and Technology of Taiwan under Grant 104-2911-I-006-534 and Grant 105-2911-I-006-508. The review of this paper was arranged by Editor F. Udrea. (Corresponding authors: Yi-Ting Wu; Meng-Hsueh Chiang.) Y.-T. Wu, M.-H. Chiang, and J. F. Chen are with the Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan City 701, Taiwan (e-mail: ytwu@eecs.berkeley.edu; mhchiang@mail.ncku.edu.tw; jfchen@mail.ncku.edu.tw). Publisher Copyright: {\textcopyright} 1963-2012 IEEE.",

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AU - Chiang, Meng Hsueh

AU - Chen, Jone F.

AU - Liu, Tsu Jae King

N1 - Funding Information: Manuscript received June 15, 2017; revised July 31, 2017; accepted August 2, 2017. Date of publication August 14, 2017; date of current version September 20, 2017. This work was supported by the Ministry of Science and Technology of Taiwan under Grant 104-2911-I-006-534 and Grant 105-2911-I-006-508. The review of this paper was arranged by Editor F. Udrea. (Corresponding authors: Yi-Ting Wu; Meng-Hsueh Chiang.) Y.-T. Wu, M.-H. Chiang, and J. F. Chen are with the Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan City 701, Taiwan (e-mail: ytwu@eecs.berkeley.edu; mhchiang@mail.ncku.edu.tw; jfchen@mail.ncku.edu.tw). Publisher Copyright: © 1963-2012 IEEE.

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Simulation-Based Study of Hybrid Fin/Planar LDMOS Design for FinFET-Based System-on-Chip Technology

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