Simulation-Based Study of Hybrid Fin/Planar LDMOS Design for FinFET-Based System-on-Chip Technology

Yi Ting Wu, Fei Ding, Daniel Connelly, Peng Zheng, Meng Hsueh Chiang, Jone F. Chen, Tsu Jae King Liu

Research output: Contribution to journalArticlepeer-review

24 Citations (Scopus)


A hybrid fin/planar lateral double-diffused MOSFET (LDMOS) design (hybrid FET) is proposed for the high-voltage input-output devices in a FinFET-based system-on-chip (SoC) technology. 3-D technology computer-aided design simulations show that a planar drift region and a planar drain region are advantageous for higher breakdown voltage (BV) to specific on-state resistance (R on\ sp) ratio (BV2/ R on\ sp). By slightly extending the planar portion of the semiconductor active region into the gated channel region, the theoretical limit of BV2/ R on\ sp for LDMOS can be surpassed. Hybrid FETs can be fabricated using a process flow that is compatible with the state-of-art FinFET SoC technology.

Original languageEnglish
Article number8010312
Pages (from-to)4193-4199
Number of pages7
JournalIEEE Transactions on Electron Devices
Issue number10
Publication statusPublished - 2017 Oct

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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