Simulation-based test algorithm generation for random access memories

Chi Feng Wu, Chih Tsun Huang, Kuo Liang Cheng, Cheng Wen Wu

Research output: Contribution to conferencePaperpeer-review

41 Citations (Scopus)


Although there are well known test algorithms that have been used by the industry for years for testing semiconductor random-access memories (RAMs), systematic evaluation of their effectiveness and efficiency has been a difficult job. In the past, it was mainly done manually by proving a certain algorithm can detect a certain type of fault. As memory technology keeps innovating, the growing complexity of the memories and number of fault types that need to be covered will require more effective and efficient test algorithms to be discovered in much shorter time. A systematic approach for developing and evaluating memory test algorithms is thus desired. We propose such an approach here: test algorithm generation by simulation (TAGS), which generates, and optimizes test algorithms, given a test time budget. Experimental results show that the algorithms generated by TAGS are more efficient than the traditional test algorithms. Using TAGS, a series of test algorithms with a detailed list of faults covered by each algorithm can be generated, providing easy trade-off between test time and fault coverage.

Original languageEnglish
Number of pages6
Publication statusPublished - 2000 Jan 1
Event18th IEEE VLSI Test Symposium (VTS-2000) - Montreal, Que, Can
Duration: 2000 Apr 302000 May 4


Conference18th IEEE VLSI Test Symposium (VTS-2000)
CityMontreal, Que, Can

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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