Simultaneous partitioning, scheduling and allocation for synthesis of multi-chip module architectures

Raghavi V. Cherabuddi, Lih-Yih Chiou, Magdy A. Bayoumi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present a simultaneous partitioning, scheduling and allocation technique for the synthesis of multi-chip module architectures. It is based on the Stochastic Evolution heuristic, which is an effective heuristic for solving several combinatorial optimization problems. Before the actual partitioning is performed, Supernodes are created based on the scheduling/allocation constraints which in turn reduces the search space for the partitioner. We formulate the partitioning problem as an extension to the Network-Bisectioning problem for which the Stochastic Evolution heuristic has been shown to provide better results than the Simulated Annealing technique. Scheduling/Allocation and Pin Sharing are also performed simultaneously with partitioning to estimate the area and pincount requirements for each of the partitions. Efficient partitions are obtained for some of the digital signal processing applications in reasonable CPU time.

Original languageEnglish
Title of host publicationProceedings of the International Conference on the Economics of Design, Test, and Manufacturing
PublisherIEEE
Pages129-135
Number of pages7
Publication statusPublished - 1996
EventProceedings of the 1994 3rd International Conference on the Economics of Design, Test, and Manufacturing - Austin, TX, USA
Duration: 1994 May 161994 May 17

Other

OtherProceedings of the 1994 3rd International Conference on the Economics of Design, Test, and Manufacturing
CityAustin, TX, USA
Period94-05-1694-05-17

All Science Journal Classification (ASJC) codes

  • Economics, Econometrics and Finance(all)
  • General Engineering

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