A 1024-point single-bin discrete Fourier transform (SBDFT)-based digital calibration technique is presented for high-performance, full-code successive approximation (SAR) analog-to-digital converters (ADCs). This proposed method can evaluate the radix error in capacitor-DAC (CDAC), which deviates from the designed value. Thus, the corrected digital output codes are generated to compensate the error, thereby reducing the harmonic distortion caused by capacitor mismatch. Moreover, the proposed algorithm adopts a recursive SBDFT computation rather than a conventional fast Fourier transform (FFT) computation methods because the simple hardware, which reduces hardware complexity and power consumption, can be achieved to calculate a certain bin in this work. The effective number of bits (ENOB) and signal-to-noise ratio (SNDR) can be enhanced by approximately 2 bits and 14.52 dB, respectively, on the basis of the simulation result of a 12-bit SAR ADC behavior model with 0.3% capacitor mismatch. The proposed SAR ADC is fabricated in TSMC 0.18μ m 1P6M technology. Measurement results explain that the SNDR, spurious free dynamic range, and ENOB are 46.49/67.28 dB, 49.66/80.73 dB, and 7.43/10.88 bits before/after calibration, respectively, wherein the power supply is 3.3 V and the input signal frequency is 2 kHz with a sampling rate of 100 kS/s.
|Number of pages||10|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|Publication status||Published - 2019 Dec|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering