Abstract
This study proposes a single bit-line and disturbance-free static random-access memory (SRAM) cell for ultra-low voltage applications. SRAM cell with read-decoupled and cross-point structure addresses both the read-disturb and half-select stability issues; nevertheless, the write-ability is degraded due to the stacked pass transistors. In this study, the authors propose a single-ended 8T bit-cell and dual word-line control technique that can simultaneously improve the read stability, half-select stability, and write-ability without additional peripheral circuits, which is advantageous for bit-interleaved ultra-low voltage operations. A 4 kb test chip was implemented in a 90 nm complementary metal-oxide-semiconductor process to verify the proposed design. Silicon measurements indicate that the proposed design can operate at a voltage as low as 360 mV with 2.68 μW power consumption.
| Original language | English |
|---|---|
| Pages (from-to) | 713-719 |
| Number of pages | 7 |
| Journal | IET Circuits, Devices and Systems |
| Volume | 12 |
| Issue number | 6 |
| DOIs | |
| Publication status | Published - 2018 Nov 1 |
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All Science Journal Classification (ASJC) codes
- Control and Systems Engineering
- Electrical and Electronic Engineering
Cite this
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Single bit-line 8T SRAM cell with asynchronous dual word-line control for bitinterleaved ultra-low voltage operation. / Huang, Chi Ray; Chiou, Lih-Yih.
In: IET Circuits, Devices and Systems, Vol. 12, No. 6, 01.11.2018, p. 713-719.Research output: Contribution to journal › Article
TY - JOUR
T1 - Single bit-line 8T SRAM cell with asynchronous dual word-line control for bitinterleaved ultra-low voltage operation
AU - Huang, Chi Ray
AU - Chiou, Lih-Yih
PY - 2018/11/1
Y1 - 2018/11/1
N2 - This study proposes a single bit-line and disturbance-free static random-access memory (SRAM) cell for ultra-low voltage applications. SRAM cell with read-decoupled and cross-point structure addresses both the read-disturb and half-select stability issues; nevertheless, the write-ability is degraded due to the stacked pass transistors. In this study, the authors propose a single-ended 8T bit-cell and dual word-line control technique that can simultaneously improve the read stability, half-select stability, and write-ability without additional peripheral circuits, which is advantageous for bit-interleaved ultra-low voltage operations. A 4 kb test chip was implemented in a 90 nm complementary metal-oxide-semiconductor process to verify the proposed design. Silicon measurements indicate that the proposed design can operate at a voltage as low as 360 mV with 2.68 μW power consumption.
AB - This study proposes a single bit-line and disturbance-free static random-access memory (SRAM) cell for ultra-low voltage applications. SRAM cell with read-decoupled and cross-point structure addresses both the read-disturb and half-select stability issues; nevertheless, the write-ability is degraded due to the stacked pass transistors. In this study, the authors propose a single-ended 8T bit-cell and dual word-line control technique that can simultaneously improve the read stability, half-select stability, and write-ability without additional peripheral circuits, which is advantageous for bit-interleaved ultra-low voltage operations. A 4 kb test chip was implemented in a 90 nm complementary metal-oxide-semiconductor process to verify the proposed design. Silicon measurements indicate that the proposed design can operate at a voltage as low as 360 mV with 2.68 μW power consumption.
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U2 - 10.1049/iet-cds.2018.5150
DO - 10.1049/iet-cds.2018.5150
M3 - Article
VL - 12
SP - 713
EP - 719
JO - IET Circuits, Devices and Systems
JF - IET Circuits, Devices and Systems
SN - 1751-858X
IS - 6
ER -