Single bit-line 8T SRAM cell with asynchronous dual word-line control for bitinterleaved ultra-low voltage operation

Chi Ray Huang, Lih-Yih Chiou

Research output: Contribution to journalArticle

Abstract

This study proposes a single bit-line and disturbance-free static random-access memory (SRAM) cell for ultra-low voltage applications. SRAM cell with read-decoupled and cross-point structure addresses both the read-disturb and half-select stability issues; nevertheless, the write-ability is degraded due to the stacked pass transistors. In this study, the authors propose a single-ended 8T bit-cell and dual word-line control technique that can simultaneously improve the read stability, half-select stability, and write-ability without additional peripheral circuits, which is advantageous for bit-interleaved ultra-low voltage operations. A 4 kb test chip was implemented in a 90 nm complementary metal-oxide-semiconductor process to verify the proposed design. Silicon measurements indicate that the proposed design can operate at a voltage as low as 360 mV with 2.68 μW power consumption.

Original languageEnglish
Pages (from-to)713-719
Number of pages7
JournalIET Circuits, Devices and Systems
Volume12
Issue number6
DOIs
Publication statusPublished - 2018 Nov 1

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Data storage equipment
Electric potential
Transistors
Electric power utilization
Silicon
Networks (circuits)
Metals
Oxide semiconductors

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

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abstract = "This study proposes a single bit-line and disturbance-free static random-access memory (SRAM) cell for ultra-low voltage applications. SRAM cell with read-decoupled and cross-point structure addresses both the read-disturb and half-select stability issues; nevertheless, the write-ability is degraded due to the stacked pass transistors. In this study, the authors propose a single-ended 8T bit-cell and dual word-line control technique that can simultaneously improve the read stability, half-select stability, and write-ability without additional peripheral circuits, which is advantageous for bit-interleaved ultra-low voltage operations. A 4 kb test chip was implemented in a 90 nm complementary metal-oxide-semiconductor process to verify the proposed design. Silicon measurements indicate that the proposed design can operate at a voltage as low as 360 mV with 2.68 μW power consumption.",
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Single bit-line 8T SRAM cell with asynchronous dual word-line control for bitinterleaved ultra-low voltage operation. / Huang, Chi Ray; Chiou, Lih-Yih.

In: IET Circuits, Devices and Systems, Vol. 12, No. 6, 01.11.2018, p. 713-719.

Research output: Contribution to journalArticle

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