TY - JOUR
T1 - Single mask dual damascene processes
AU - Perng, Dung Ching
AU - Fang, Jia Feng
AU - Chen, Jhin Wei
N1 - Funding Information:
The authors are grateful to KLA-Tencor for sponsorship of the PROLITH v.9.2 simulation software. We also would like to acknowledge the financial support of the National Science Council (NSC) of Taiwan, ROC under Contract No. NSC 95-2221-E-006-427.
Copyright:
Copyright 2008 Elsevier B.V., All rights reserved.
PY - 2008/3
Y1 - 2008/3
N2 - Single mask dual damascene processes are described. The unique mask merges via and modified trench patterns. We design the mask's trench area to have partial transmission using thin chromium or add phase shifted gratings in the trench area to achieve destructive interference for lowering the intensity. Optical proximity correction is used to obtain the desired lithography process window. Upon exposure, the trench results in a partial exposure while the via is fully exposed and a dual damascene (DD) photoresist profile is created within specifications. Following with an integrated etch can complete the DD image transfer into the underneath dielectric. A single mask DD process eliminates via/trench misalignment issues, can save up to one half of metal mask cost, and 50% of other processing costs. It is expected to also boost yield and improve product reliability.
AB - Single mask dual damascene processes are described. The unique mask merges via and modified trench patterns. We design the mask's trench area to have partial transmission using thin chromium or add phase shifted gratings in the trench area to achieve destructive interference for lowering the intensity. Optical proximity correction is used to obtain the desired lithography process window. Upon exposure, the trench results in a partial exposure while the via is fully exposed and a dual damascene (DD) photoresist profile is created within specifications. Following with an integrated etch can complete the DD image transfer into the underneath dielectric. A single mask DD process eliminates via/trench misalignment issues, can save up to one half of metal mask cost, and 50% of other processing costs. It is expected to also boost yield and improve product reliability.
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U2 - 10.1016/j.mee.2007.11.003
DO - 10.1016/j.mee.2007.11.003
M3 - Article
AN - SCOPUS:39149145548
VL - 85
SP - 599
EP - 602
JO - Microelectronic Engineering
JF - Microelectronic Engineering
SN - 0167-9317
IS - 3
ER -