Single polysilicon gate high-density logic using independently-controlled double-gate devices

Meng Hsueh Chiang, Keunwoo Kim, Ching Te Chuang, Christophe Tretz

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Novel double-gate (DG) CMOS logic with a single polysilicon gate process is proposed using independently biased gates. The unique gate-to-gate coupling of DG devices is exploited to improve circuit density, capacitance, performance, and power in 25 nm logic circuits by halving the number of stacked transistors as well as parallel transistors for implementing logic functions. The performance, power, and design trade-offs as well as layouts for logic gates are analyzed via mixed-mode two-dimensional numerical simulations.

Original languageEnglish
Title of host publication2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
PublisherIEEE Computer Society
Pages353-356
Number of pages4
ISBN (Print)0780391624, 9780780391628
DOIs
Publication statusPublished - 2005 Jan 1
Event1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005 - Hsinchu, Taiwan
Duration: 2005 Nov 12005 Nov 3

Publication series

Name2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Other

Other1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005
CountryTaiwan
CityHsinchu
Period05-11-0105-11-03

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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    Chiang, M. H., Kim, K., Chuang, C. T., & Tretz, C. (2005). Single polysilicon gate high-density logic using independently-controlled double-gate devices. In 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005 (pp. 353-356). [4017604] (2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005). IEEE Computer Society. https://doi.org/10.1109/ASSCC.2005.251738