TY - JOUR
T1 - SKB-tree
T2 - A fixed-outline driven representation for modern floorplanning problems
AU - Lin, Jai Ming
AU - Hung, Zhi Xiong
N1 - Funding Information:
Manuscript received March 18, 2010; revised July 10, 2010 and October 24, 2010; accepted December 15, 2010. Date of publication February 04, 2011; date of current version February 17, 2012. This work was supported by the National Science Council of Taiwan under Grant 99-2220-E-006-019.
PY - 2012/3
Y1 - 2012/3
N2 - In this paper, we propose an SKB-tree representation for two modern floorplaning problems: fixed-outline and voltage-island driven floorplanning. Since SKB-tree can dynamically allocate regions for blocks so that all blocks can be placed into a specific outline for each solution, it is a suitable representation for dealing with the fixed-outline constraint. Due to this good property, we also use it to deal with the voltage-island driven floorplanning. Different from previous works, we constrain blocks of the same voltage to be placed into one region to save power routing resource, simplify power planning, and reduce IR Drop. Experimental results show the feasibility of SKB-tree. For the fixed-outline constraint with zero deadspace, SKB-tree achieved significantly better wirelength than A-FP, Parquet 4.0, ZDS, and SAFFOA. SKB-tree can get better results than other fixed-outline driven floorplanners because it only needs to focus on wirelength optimization during simulated annealing. Besides, for voltage island driven floorplanning, SKB-tree also consumes less power and wirelength.
AB - In this paper, we propose an SKB-tree representation for two modern floorplaning problems: fixed-outline and voltage-island driven floorplanning. Since SKB-tree can dynamically allocate regions for blocks so that all blocks can be placed into a specific outline for each solution, it is a suitable representation for dealing with the fixed-outline constraint. Due to this good property, we also use it to deal with the voltage-island driven floorplanning. Different from previous works, we constrain blocks of the same voltage to be placed into one region to save power routing resource, simplify power planning, and reduce IR Drop. Experimental results show the feasibility of SKB-tree. For the fixed-outline constraint with zero deadspace, SKB-tree achieved significantly better wirelength than A-FP, Parquet 4.0, ZDS, and SAFFOA. SKB-tree can get better results than other fixed-outline driven floorplanners because it only needs to focus on wirelength optimization during simulated annealing. Besides, for voltage island driven floorplanning, SKB-tree also consumes less power and wirelength.
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U2 - 10.1109/TVLSI.2011.2104983
DO - 10.1109/TVLSI.2011.2104983
M3 - Article
AN - SCOPUS:84857452857
SN - 1063-8210
VL - 20
SP - 473
EP - 484
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 3
M1 - 5710024
ER -