Skew and delay minimization of high speed CMOS circuits using stochastic optimization

For certain high speed CMOS circuits, e.g. clock drivers, wave-pipelined circuits, it is very important to limit the spread in circuit delay as well as the worst-case delay. The delay spread, or skew, is caused by the data-dependency of the circuit delay. To reduce the effect of process and environmental variations on skew and circuit delay, the transistors in a CMOS circuit need to be carefully sized. In this paper, we present a stochastic optimization approach to transistor sizing. Each sizing scheme considered during optimization is evaluated through accurate circuit simulations to determine the delay and skew values. The power of the optimization technique enables us to generate very good sizing schemes with few simulations, as demonstrated by the example given here.