Soc testing and design for testability

Integrating reusable cores from multiple sources is essential in system-on-chip (SOC) design. Testing these cores as well as the integrated system chip requires not just the conventional design-for-testability (DFT) methodologies, but also new ones. SOC testing involves applying test patterns to and analyzing the corresponding response from each and every core. In addition, the user-defined logic as well as the final integrated chip has to be tested. There are new challenges and issues, such as core isolation, test access, test pattern translation (from core to chip), test integration and scheduling, test automation, etc. This chapter discusses in detail the challenges and solutions in core-based SOC testing. We also briefly describe the IEEE 1500 that standardizes the test interface (called the Test Wrapper) between a core and its SOC host, and the Core Test Language (CTL) for test automation. We present a novel SOC test integration platform, solving real problems in test scheduling, test IO reduction, timing of functional test, scan IO sharing, embedded memory built-in self-test (BIST), etc. We also present a memory BIST compiler that provides a complete solution for SOCs with heterogeneous memory cores