SOC testing methodology and practice

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)


On a commercial digital still camera (DSC) controller chip we practice a novel SOC test integration platform, solving real problems in test scheduling, test IO reduction, timing of functional test, scan IO sharing, embedded memory built-in self-test (BIST), etc. The chip has been fabricated and tested successfully by our approach. Test results justify that short test integration cost, short test time, and small area overhead can be achieved. To support SOC testing, a memory BIST compiler and an SOC testing integration system have been developed.

Original languageEnglish
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE '05
Number of pages2
Publication statusPublished - 2005 Dec 1
EventDesign, Automation and Test in Europe, DATE '05 - Munich, Germany
Duration: 2005 Mar 72005 Mar 11

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE '05
ISSN (Print)1530-1591


ConferenceDesign, Automation and Test in Europe, DATE '05

All Science Journal Classification (ASJC) codes

  • Engineering(all)


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