Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits

Erik Jan Marinissen, Ferenc Fodor, Arnita Podpod, Michele Stucchi, Yu Rong Jian, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Multi-die stacked ICs are getting increasing traction in the market, fueled by innovations in wafer processing technologies (e.g., vertical inter-die and intra-die connections), stack assembly, and advanced packaging approaches (e.g., wafer-level packaging). Given the non-perfect nature of their manufacturing processes, these stacked ICs (SICs) need all to be individually tested for manufacturing defects in an effective, yet efficient manner. This paper discusses a handful of probing challenges specific to such SICs and their solutions: probing ultra-thin wafers on a flexible tape on extra-large tape frames, probing on large arrays of dense micro-bumps, analyzing probe-to-pad alignment (PTPA) accuracy contributions from probe station and probe card on the basis of probe mark images, and efficient auto-correction of individual misalignments of singulated dies or die stacks on tape. The paper concludes with a real-life case study, in which most of the discussed challenges and solutions are combined.

Original languageEnglish
Title of host publicationInternational Test Conference 2018, ITC 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538683828
DOIs
Publication statusPublished - 2019 Jan 23
Event49th IEEE International Test Conference, ITC 2018 - Phoenix, United States
Duration: 2018 Oct 292018 Nov 1

Publication series

NameProceedings - International Test Conference
Volume2018-October
ISSN (Print)1089-3539

Conference

Conference49th IEEE International Test Conference, ITC 2018
CountryUnited States
CityPhoenix
Period18-10-2918-11-01

Fingerprint

Integrated Circuits
Integrated circuits
Die
Probe
Wafer
Tapes
Packaging
Manufacturing
Misalignment
Alignment
Defects
Innovation
Vertical
Processing

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

Marinissen, E. J., Fodor, F., Podpod, A., Stucchi, M., Jian, Y. R., & Wu, C. W. (2019). Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits. In International Test Conference 2018, ITC 2018 - Proceedings [8624731] (Proceedings - International Test Conference; Vol. 2018-October). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TEST.2018.8624731
Marinissen, Erik Jan ; Fodor, Ferenc ; Podpod, Arnita ; Stucchi, Michele ; Jian, Yu Rong ; Wu, Cheng Wen. / Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits. International Test Conference 2018, ITC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. (Proceedings - International Test Conference).
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Marinissen, EJ, Fodor, F, Podpod, A, Stucchi, M, Jian, YR & Wu, CW 2019, Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits. in International Test Conference 2018, ITC 2018 - Proceedings., 8624731, Proceedings - International Test Conference, vol. 2018-October, Institute of Electrical and Electronics Engineers Inc., 49th IEEE International Test Conference, ITC 2018, Phoenix, United States, 18-10-29. https://doi.org/10.1109/TEST.2018.8624731

Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits. / Marinissen, Erik Jan; Fodor, Ferenc; Podpod, Arnita; Stucchi, Michele; Jian, Yu Rong; Wu, Cheng Wen.

International Test Conference 2018, ITC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. 8624731 (Proceedings - International Test Conference; Vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Marinissen EJ, Fodor F, Podpod A, Stucchi M, Jian YR, Wu CW. Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits. In International Test Conference 2018, ITC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2019. 8624731. (Proceedings - International Test Conference). https://doi.org/10.1109/TEST.2018.8624731