TY - GEN
T1 - Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications
AU - Huang, Ya Chi
AU - Chiang, Meng Hsueh
AU - Wang, Shui Jinn
N1 - Funding Information:
This work was partially supported by the Ministry of Science and Technology of Taiwan. The authors would like to thank National Center for High-Performance Computing, National Chip Implementation Center, and Nano Device Laboratories for technical support.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/4/23
Y1 - 2019/4/23
N2 - This paper proposes vertically stacked gate-all-around MOSFET structure with optimized inner spacers to provide superior gate controllability and reduce additional parasitic capacitance simultaneously. To achieve better performance, we evaluate different inner spacer lengths while tuning source/drain doping profile to keep off-state leakage current unchanged. Considering the fabrication uniformity, the key of the conceptual process flow is to etch inner spacers selectively from top to bottom channel. The proposed approach can be applied to low power and ultra-low power design for SoC application without additional mask cost.
AB - This paper proposes vertically stacked gate-all-around MOSFET structure with optimized inner spacers to provide superior gate controllability and reduce additional parasitic capacitance simultaneously. To achieve better performance, we evaluate different inner spacer lengths while tuning source/drain doping profile to keep off-state leakage current unchanged. Considering the fabrication uniformity, the key of the conceptual process flow is to etch inner spacers selectively from top to bottom channel. The proposed approach can be applied to low power and ultra-low power design for SoC application without additional mask cost.
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U2 - 10.1109/ISQED.2019.8697706
DO - 10.1109/ISQED.2019.8697706
M3 - Conference contribution
AN - SCOPUS:85065178852
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
SP - 231
EP - 234
BT - Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019
PB - IEEE Computer Society
T2 - 20th International Symposium on Quality Electronic Design, ISQED 2019
Y2 - 6 March 2019 through 7 March 2019
ER -