Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications

Ya Chi Huang; Meng-Hsueh Chiang; Shui-Jinn Wang

doi:10.1109/ISQED.2019.8697706

Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications

Ya Chi Huang, Meng-Hsueh Chiang, Shui-Jinn Wang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper proposes vertically stacked gate-all-around MOSFET structure with optimized inner spacers to provide superior gate controllability and reduce additional parasitic capacitance simultaneously. To achieve better performance, we evaluate different inner spacer lengths while tuning source/drain doping profile to keep off-state leakage current unchanged. Considering the fabrication uniformity, the key of the conceptual process flow is to etch inner spacers selectively from top to bottom channel. The proposed approach can be applied to low power and ultra-low power design for SoC application without additional mask cost.

Original language	English
Title of host publication	Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019
Publisher	IEEE Computer Society
Pages	231-234
Number of pages	4
ISBN (Electronic)	9781728103921
DOIs	https://doi.org/10.1109/ISQED.2019.8697706
Publication status	Published - 2019 Apr 23
Event	20th International Symposium on Quality Electronic Design, ISQED 2019 - Santa Clara, United States Duration: 2019 Mar 6 → 2019 Mar 7

Publication series

Name	Proceedings - International Symposium on Quality Electronic Design, ISQED
Volume	2019-March
ISSN (Print)	1948-3287
ISSN (Electronic)	1948-3295

Conference

Conference	20th International Symposium on Quality Electronic Design, ISQED 2019
Country	United States
City	Santa Clara
Period	19-03-06 → 19-03-07

Fingerprint

Controllability

Leakage currents

Masks

Capacitance

Tuning

Doping (additives)

Fabrication

Costs

System-on-chip

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Cite this

Huang, Y. C., Chiang, M-H., & Wang, S-J. (2019). Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications. In Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019 (pp. 231-234). [8697706] (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2019-March). IEEE Computer Society. https://doi.org/10.1109/ISQED.2019.8697706

Huang, Ya Chi ; Chiang, Meng-Hsueh ; Wang, Shui-Jinn. / Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications. Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019. IEEE Computer Society, 2019. pp. 231-234 (Proceedings - International Symposium on Quality Electronic Design, ISQED).

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abstract = "This paper proposes vertically stacked gate-all-around MOSFET structure with optimized inner spacers to provide superior gate controllability and reduce additional parasitic capacitance simultaneously. To achieve better performance, we evaluate different inner spacer lengths while tuning source/drain doping profile to keep off-state leakage current unchanged. Considering the fabrication uniformity, the key of the conceptual process flow is to etch inner spacers selectively from top to bottom channel. The proposed approach can be applied to low power and ultra-low power design for SoC application without additional mask cost.",

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Huang, YC, Chiang, M-H & Wang, S-J 2019, Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications. in Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019., 8697706, Proceedings - International Symposium on Quality Electronic Design, ISQED, vol. 2019-March, IEEE Computer Society, pp. 231-234, 20th International Symposium on Quality Electronic Design, ISQED 2019, Santa Clara, United States, 19-03-06. https://doi.org/10.1109/ISQED.2019.8697706

Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications. / Huang, Ya Chi; Chiang, Meng-Hsueh ; Wang, Shui-Jinn.

Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019. IEEE Computer Society, 2019. p. 231-234 8697706 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2019-March).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Huang YC, Chiang M-H , Wang S-J. Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications. In Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019. IEEE Computer Society. 2019. p. 231-234. 8697706. (Proceedings - International Symposium on Quality Electronic Design, ISQED). https://doi.org/10.1109/ISQED.2019.8697706

Access to Document

10.1109/ISQED.2019.8697706