Speed superiority of scaled double-gate CMOS

Jerry G. Fossum, Lixin Ge, Meng Hsueh Chiang

Research output: Contribution to journalArticlepeer-review

71 Citations (Scopus)


Unloaded ring-oscillator simulations, done with a generic process/physics-based compact model for double-gate (DG) MOSFETs and supplemented with model-predicted on-state currents and gate capacitances for varying supply voltages (V DDD), are used to show and explain the speed superiority of extremely scaled DG CMOS over the single-gate (e.g., bulk-Si) counterpart. The DG superiority for unloaded circuits is most substantive for low V DD < ∼1 V.

Original languageEnglish
Pages (from-to)808-811
Number of pages4
JournalIEEE Transactions on Electron Devices
Issue number5
Publication statusPublished - 2002 May

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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