Speeding up emulation-based diagnosis techniques for logic cores

Shyue Kung Lu; Yin Mou Chen; Shi Yu Huang; Cheng Wen Wu

doi:10.1109/MDT.2011.25

Speeding up emulation-based diagnosis techniques for logic cores

Shyue Kung Lu, Yin Mou Chen, Shi Yu Huang, Cheng Wen Wu

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

This article proposes a new approach for an FPGA-based emulation system for IC fault diagnosis that incorporates three speedup techniques: circuit partitioning, fault-injection elements (using a novel design), and a fault-injection scan chain. Experimental results in terms of hardware overhead and emulation time for ISCAS-85 benchmark circuits are compared with previous works to highlight the 33× speedup and 44% reduced overhead of this proposed system.

Original language	English
Article number	5728786
Pages (from-to)	88-97
Number of pages	10
Journal	IEEE Design and Test of Computers
Volume	28
Issue number	4
DOIs	https://doi.org/10.1109/MDT.2011.25
Publication status	Published - 2011 Jul 1

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Software
Electrical and Electronic Engineering

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10.1109/MDT.2011.25

Cite this

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abstract = "This article proposes a new approach for an FPGA-based emulation system for IC fault diagnosis that incorporates three speedup techniques: circuit partitioning, fault-injection elements (using a novel design), and a fault-injection scan chain. Experimental results in terms of hardware overhead and emulation time for ISCAS-85 benchmark circuits are compared with previous works to highlight the 33× speedup and 44% reduced overhead of this proposed system.",

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Speeding up emulation-based diagnosis techniques for logic cores

Abstract

All Science Journal Classification (ASJC) codes

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