Speeding up emulation-based diagnosis techniques for logic cores

Shyue Kung Lu, Yin Mou Chen, Shi Yu Huang, Cheng Wen Wu

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)

Abstract

This article proposes a new approach for an FPGA-based emulation system for IC fault diagnosis that incorporates three speedup techniques: circuit partitioning, fault-injection elements (using a novel design), and a fault-injection scan chain. Experimental results in terms of hardware overhead and emulation time for ISCAS-85 benchmark circuits are compared with previous works to highlight the 33× speedup and 44% reduced overhead of this proposed system.

Original languageEnglish
Article number5728786
Pages (from-to)88-97
Number of pages10
JournalIEEE Design and Test of Computers
Volume28
Issue number4
DOIs
Publication statusPublished - 2011 Jul 1

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Speeding up emulation-based diagnosis techniques for logic cores'. Together they form a unique fingerprint.

Cite this