Abstract
This article proposes a new approach for an FPGA-based emulation system for IC fault diagnosis that incorporates three speedup techniques: circuit partitioning, fault-injection elements (using a novel design), and a fault-injection scan chain. Experimental results in terms of hardware overhead and emulation time for ISCAS-85 benchmark circuits are compared with previous works to highlight the 33× speedup and 44% reduced overhead of this proposed system.
Original language | English |
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Article number | 5728786 |
Pages (from-to) | 88-97 |
Number of pages | 10 |
Journal | IEEE Design and Test of Computers |
Volume | 28 |
Issue number | 4 |
DOIs | |
Publication status | Published - 2011 Jul 1 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Software
- Electrical and Electronic Engineering