Speeding up emulation-based diagnosis techniques for logic cores

Shyue Kung Lu; Yin Mou Chen; Shi Yu Huang; Cheng Wen Wu

doi:10.1109/MDT.2011.25

Speeding up emulation-based diagnosis techniques for logic cores

Shyue Kung Lu, Yin Mou Chen, Shi Yu Huang, Cheng Wen Wu

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

This article proposes a new approach for an FPGA-based emulation system for IC fault diagnosis that incorporates three speedup techniques: circuit partitioning, fault-injection elements (using a novel design), and a fault-injection scan chain. Experimental results in terms of hardware overhead and emulation time for ISCAS-85 benchmark circuits are compared with previous works to highlight the 33× speedup and 44% reduced overhead of this proposed system.

Original language	English
Article number	5728786
Pages (from-to)	88-97
Number of pages	10
Journal	IEEE Design and Test of Computers
Volume	28
Issue number	4
DOIs	https://doi.org/10.1109/MDT.2011.25
Publication status	Published - 2011 Jul 1

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Software
Electrical and Electronic Engineering

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@article{220f15032f464436ba973565529ca721,

title = "Speeding up emulation-based diagnosis techniques for logic cores",

abstract = "This article proposes a new approach for an FPGA-based emulation system for IC fault diagnosis that incorporates three speedup techniques: circuit partitioning, fault-injection elements (using a novel design), and a fault-injection scan chain. Experimental results in terms of hardware overhead and emulation time for ISCAS-85 benchmark circuits are compared with previous works to highlight the 33× speedup and 44% reduced overhead of this proposed system.",

author = "Lu, {Shyue Kung} and Chen, {Yin Mou} and Huang, {Shi Yu} and Wu, {Cheng Wen}",

year = "2011",

month = jul,

day = "1",

doi = "10.1109/MDT.2011.25",

language = "English",

volume = "28",

pages = "88--97",

journal = "IEEE Design and Test",

issn = "2168-2356",

publisher = "IEEE Computer Society",

number = "4",

}

TY - JOUR

T1 - Speeding up emulation-based diagnosis techniques for logic cores

AU - Lu, Shyue Kung

AU - Chen, Yin Mou

AU - Huang, Shi Yu

AU - Wu, Cheng Wen

PY - 2011/7/1

Y1 - 2011/7/1

N2 - This article proposes a new approach for an FPGA-based emulation system for IC fault diagnosis that incorporates three speedup techniques: circuit partitioning, fault-injection elements (using a novel design), and a fault-injection scan chain. Experimental results in terms of hardware overhead and emulation time for ISCAS-85 benchmark circuits are compared with previous works to highlight the 33× speedup and 44% reduced overhead of this proposed system.

AB - This article proposes a new approach for an FPGA-based emulation system for IC fault diagnosis that incorporates three speedup techniques: circuit partitioning, fault-injection elements (using a novel design), and a fault-injection scan chain. Experimental results in terms of hardware overhead and emulation time for ISCAS-85 benchmark circuits are compared with previous works to highlight the 33× speedup and 44% reduced overhead of this proposed system.

UR - http://www.scopus.com/inward/record.url?scp=84055224778&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84055224778&partnerID=8YFLogxK

U2 - 10.1109/MDT.2011.25

DO - 10.1109/MDT.2011.25

M3 - Article

AN - SCOPUS:84055224778

VL - 28

SP - 88

EP - 97

JO - IEEE Design and Test

JF - IEEE Design and Test

SN - 2168-2356

IS - 4

M1 - 5728786

ER -