Spin wave nanofabric update

J. G. Alzate, P. Upadhyaya, M. Lewis, J. Nath, Y. T. Lin, K. Wong, S. Cherepov, P. Khalili Amiri, K. L. Wang, J. Hockel, A. Bur, G. P. Carman, S. Bender, Y. Tserkovnyak, J. Zhu, Y. J. Chen, I. N. Krivorotov, J. Katine, J. Langer, P. ShabadiS. Khasanvis, S. Narayanan, C. A. Moritz, A. Khitun

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)

Abstract

We provide a progress update on the spin wave nanofabric. The nanofabric comprises magneto-electric cells and spin wave buses serving for spin wave propagation. The magneto-electric cells are used as the input/output ports for information transfer between the charge and the spin domains, while information processing inside the nanofabric is via spin waves only. Information is encoded into the phase of the propagating spin wave, which makes it possible to utilize waveguides as passive logic elements and take the advantage of using wave superposition for data processing. This provides a fundamental advantage over the conventional transistor-based logic circuitry allowing for functional throughput enhancement and power consumption minimization at the same time. We present recent accomplishments in the magneto-electric element development and integration with spin wave buses. In particular, we show the excitation and detection of the spin waves via multiferroic elements. In addition, we present different approaches to magnonic logic circuit engineering and provide the comparison with CMOS by mapping the designs to 45nm NANGATE standard cell libraries. The estimates show more than 40X power reduction and 53X area reduction for magnonic circuits. These results illustrate the potential advantages over conventional charge based electronics that could be a route to beyond CMOS logic circuitry.

Original languageEnglish
Title of host publicationProceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012
PublisherIEEE Computer Society
Pages196-202
Number of pages7
ISBN (Print)9781450316712
DOIs
Publication statusPublished - 2012
Event2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012 - Amsterdam, Netherlands
Duration: 2012 Jul 42012 Jul 6

Publication series

NameProceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012

Conference

Conference2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012
CountryNetherlands
CityAmsterdam
Period12-07-0412-07-06

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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