With the advent of deep-submicron VLSI technologies, the working speed of SRAM circuits has grown to a level that at-speed testing of SRAM has become an important issue. In this paper, we present delay fault models for SRAM, i.e., the faults that affect the access time of the SRAM circuit. We also develop the test algorithm that detects these faults. The proposed SRAM delay-fault test algorithm has a complexity of 3N + 2k Read/Write operations, where N is the number of words and k is the word count in a row.
|Number of pages||6|
|Publication status||Published - 2004 Jun 1|
|Event||Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan|
Duration: 2004 Jan 27 → 2004 Jan 30
|Conference||Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004|
|Period||04-01-27 → 04-01-30|
All Science Journal Classification (ASJC) codes