SRAM delay fault modeling and test algorithm development

Rei Fu Huang, Yan Ting Lai, Yung Fa Chou, Cheng Wen Wu

Research output: Contribution to conferencePaper

4 Citations (Scopus)

Abstract

With the advent of deep-submicron VLSI technologies, the working speed of SRAM circuits has grown to a level that at-speed testing of SRAM has become an important issue. In this paper, we present delay fault models for SRAM, i.e., the faults that affect the access time of the SRAM circuit. We also develop the test algorithm that detects these faults. The proposed SRAM delay-fault test algorithm has a complexity of 3N + 2k Read/Write operations, where N is the number of words and k is the word count in a row.

Original languageEnglish
Pages104-109
Number of pages6
Publication statusPublished - 2004 Jun 1
EventProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan
Duration: 2004 Jan 272004 Jan 30

Conference

ConferenceProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
CountryJapan
CityYokohama
Period04-01-2704-01-30

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Huang, R. F., Lai, Y. T., Chou, Y. F., & Wu, C. W. (2004). SRAM delay fault modeling and test algorithm development. 104-109. Paper presented at Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, Yokohama, Japan.