SRAM delay fault modeling and test algorithm development

Rei Fu Huang; Yan Ting Lai; Yung Fa Chou; Cheng Wen Wu

SRAM delay fault modeling and test algorithm development

Rei Fu Huang, Yan Ting Lai, Yung Fa Chou, Cheng Wen Wu

Department of Electrical Engineering

Research output: Contribution to conference › Paper › peer-review

4 Citations (Scopus)

Abstract

With the advent of deep-submicron VLSI technologies, the working speed of SRAM circuits has grown to a level that at-speed testing of SRAM has become an important issue. In this paper, we present delay fault models for SRAM, i.e., the faults that affect the access time of the SRAM circuit. We also develop the test algorithm that detects these faults. The proposed SRAM delay-fault test algorithm has a complexity of 3N + 2k Read/Write operations, where N is the number of words and k is the word count in a row.

Original language	English
Pages	104-109
Number of pages	6
Publication status	Published - 2004 Jun 1
Event	Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan Duration: 2004 Jan 27 → 2004 Jan 30

Conference

Conference	Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
Country	Japan
City	Yokohama
Period	04-01-27 → 04-01-30

All Science Journal Classification (ASJC) codes

Engineering(all)

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Cite this

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title = "SRAM delay fault modeling and test algorithm development",

abstract = "With the advent of deep-submicron VLSI technologies, the working speed of SRAM circuits has grown to a level that at-speed testing of SRAM has become an important issue. In this paper, we present delay fault models for SRAM, i.e., the faults that affect the access time of the SRAM circuit. We also develop the test algorithm that detects these faults. The proposed SRAM delay-fault test algorithm has a complexity of 3N + 2k Read/Write operations, where N is the number of words and k is the word count in a row.",

author = "Huang, {Rei Fu} and Lai, {Yan Ting} and Chou, {Yung Fa} and Wu, {Cheng Wen}",

year = "2004",

month = jun,

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pages = "104--109",

note = "Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 ; Conference date: 27-01-2004 Through 30-01-2004",

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AU - Huang, Rei Fu

AU - Lai, Yan Ting

AU - Chou, Yung Fa

AU - Wu, Cheng Wen

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Y1 - 2004/6/1

N2 - With the advent of deep-submicron VLSI technologies, the working speed of SRAM circuits has grown to a level that at-speed testing of SRAM has become an important issue. In this paper, we present delay fault models for SRAM, i.e., the faults that affect the access time of the SRAM circuit. We also develop the test algorithm that detects these faults. The proposed SRAM delay-fault test algorithm has a complexity of 3N + 2k Read/Write operations, where N is the number of words and k is the word count in a row.

AB - With the advent of deep-submicron VLSI technologies, the working speed of SRAM circuits has grown to a level that at-speed testing of SRAM has become an important issue. In this paper, we present delay fault models for SRAM, i.e., the faults that affect the access time of the SRAM circuit. We also develop the test algorithm that detects these faults. The proposed SRAM delay-fault test algorithm has a complexity of 3N + 2k Read/Write operations, where N is the number of words and k is the word count in a row.

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T2 - Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004

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