Abstract
A stochastic global optimization approach is presented for transistor sizing in CMOS VLSI circuits. This is a direct search strategy for the best design among feasible ones, with the designer determining when the search is stopped. Through examples, we show the power of this technique in quickly obtaining very good designs, for skew minimization problems.
Original language | English |
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Pages (from-to) | 36-40 |
Number of pages | 5 |
Journal | Proceedings - Design Automation Conference |
DOIs | |
Publication status | Published - 1994 |
Event | Proceedings of the 31st Design Automation Conference - San Diego, CA, USA Duration: 1994 Jun 6 → 1994 Jun 10 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Control and Systems Engineering