Stochastic optimization approach to transistor sizing for CMOS VLSI circuits

Sharad Mehrotra, Paul Franzon, Wentai Liu

Research output: Contribution to journalConference articlepeer-review

4 Citations (Scopus)

Abstract

A stochastic global optimization approach is presented for transistor sizing in CMOS VLSI circuits. This is a direct search strategy for the best design among feasible ones, with the designer determining when the search is stopped. Through examples, we show the power of this technique in quickly obtaining very good designs, for skew minimization problems.

Original languageEnglish
Pages (from-to)36-40
Number of pages5
JournalProceedings - Design Automation Conference
DOIs
Publication statusPublished - 1994
EventProceedings of the 31st Design Automation Conference - San Diego, CA, USA
Duration: 1994 Jun 61994 Jun 10

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering

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