Structural fault based specification reduction for testing analog circuits

Soon-Jyh Chang, Chung Len Lee, Jwu E. Chen

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is proposed and demonstrated. It starts with first deriving relationships between specifications and parameter variations of the circuit-under-test (CUT) and then reduces specifications by considering bounds of parameter variations. A statistical approach by taking into account of circuit fabrication process fluctuation is also employed and the result shows that the specification reduction depends on the testing confidence. A continuous-time state-variable benchmark filter circuit is applied with this methodology to demonstrate the effectiveness of the approach.

Original languageEnglish
Pages (from-to)571-581
Number of pages11
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Volume18
Issue number6
DOIs
Publication statusPublished - 2002 Dec 1

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Analog circuits
Specifications
Testing
Networks (circuits)
Fabrication
Costs

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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Structural fault based specification reduction for testing analog circuits. / Chang, Soon-Jyh; Lee, Chung Len; Chen, Jwu E.

In: Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 18, No. 6, 01.12.2002, p. 571-581.

Research output: Contribution to journalArticle

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