Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is proposed and demonstrated. It starts with first deriving relationships between specifications and parameter variations of the circuit-under-test (CUT) and then reduces specifications by considering bounds of parameter variations. A statistical approach by taking into account of circuit fabrication process fluctuation is also employed and the result shows that the specification reduction depends on the testing confidence. A continuous-time state-variable benchmark filter circuit is applied with this methodology to demonstrate the effectiveness of the approach.
|Number of pages||11|
|Journal||Journal of Electronic Testing: Theory and Applications (JETTA)|
|Publication status||Published - 2002 Dec|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering