Study of reducing branch penalty by hardware

Yi Chang Chen, Tsung Chuan Huang, Chu-Sing Yang, Liang Cheng Shiu

Research output: Contribution to conferencePaper

2 Citations (Scopus)

Abstract

Pipeline technique is the major method to increase the performance of single processor, but when processing branch instructions, we must wait the result of branch to decide the next instruction; we call the waiting time 'Branch Penalty', which will influence the performance of pipeline processor. Branch target buffer is an important method to resolve the branch penalty, but branch penalty occurs when the prediction incorrect. In this paper, we will propose a method to reduce the branch penalty when the prediction falls into an error on branch target buffer.

Original languageEnglish
Pages599-602
Number of pages4
Publication statusPublished - 1995 Jan 1
EventProceedings of the IEEE 1st International Conference on Algorithms and Architectures for Parallel Processing. Part 1 (of 2) - Brisbane, Aust
Duration: 1995 Apr 191995 Apr 21

Other

OtherProceedings of the IEEE 1st International Conference on Algorithms and Architectures for Parallel Processing. Part 1 (of 2)
CityBrisbane, Aust
Period95-04-1995-04-21

All Science Journal Classification (ASJC) codes

  • Computer Science(all)
  • Engineering(all)

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    Chen, Y. C., Huang, T. C., Yang, C-S., & Shiu, L. C. (1995). Study of reducing branch penalty by hardware. 599-602. Paper presented at Proceedings of the IEEE 1st International Conference on Algorithms and Architectures for Parallel Processing. Part 1 (of 2), Brisbane, Aust, .